SGU04G64A1BE1MT-BBR Datasheet, PDF (8/16 Pages) List of Unclassifed Manufacturers – 4096MB DDR3 – SDRAM UDIMM

preliminary Data Sheet
Rev.0.9 22.07.2013
Parameter
max.
& Test Condition
Symbol 12800-CL11 10600-CL9 8700-CL7 Unit
OPERATING WRITE CURRENT:
I_DD4W
1000
880
All device banks open, Continuous burst writes; One
module rank active; BL = 4, CL = CL (I_DD), AL = 0;
t_CK = t_CK (I_DD), t_RAS = t_RAS MAX (I_DD), t_RP = t_RP (I_DD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
760
mA
BURST REFRESH CURRENT:
I_DD5
t_CK = t_CK (I_DD); refresh command at every t_RFC (I_DD)
interval, CKE is HIGH, CS# is HIGH between valid
commands; All other Control and Address bus inputs
are changing once every two clock cycles; DQ inputs
changing once per clock cycle
1240
1184
1152
mA
SELF REFRESH CURRENT:
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
I_DD6
Address bus inputs are floating at V_REF; DQ’s are
floating at V_REF
OPERATING CURRENT*) :
I_DD7
Four device bank interleaving READs, I_OUT = 0mA; BL = 4,
CL = CL (I_DD), AL = t_RCD (I_DD) – 1 x t_CK (I_DD); t_CK = t_CK
(I_DD), t_RC = t_RC (I_DD), t_RRD = t_RRD (I_DD), t_RCD = t_RCD (I_DD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during
DESELECT; DQ inputs changing once per clock cycle
160
1760
160
1520
160
mA
1280
mA
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
TIMING VALUES USED FOR I_DD MEASUREMENT
SYMBOL
CL (IDD)
t_RCD (IDD)
t_RC (IDD)
t_RRD (IDD)
t_CK (IDD)
t_RAS MIN (IDD)
t_RAS MAX (IDD)
t_RP (IDD)
t_RFC (IDD)
IDD MEASUREMENT CONDITIONS
12800-CL11
10600-CL9
11
9
13.75
13.5
48.75
49.5
6
6
1.25
1.5
35
36
70’200
70’200
13.75
13.5
260
260
8700-CL7
7
13.125
50.625
7.5
1.875
37.5
70’200
13.1
260
Unit
t_CK
ns
ns
ns
ns
ns
ns
ns
ns
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: [phone]
Fax: [phone]
www.swissbit.com
eMail: [e-mail]
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