M13S128324A Datasheet, PDF (8/48 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S128324A
AC Timing Parameter & Specifications-continued
Parameter
Symbol
-5
min
max
Half Clock Period
t_HP
t_CLmin or t_CHmin
-
DQ-DQS output hold
time
t_QH
t_HP-0.45
-
ACTIVE to PRECHARGE
command
t_RAS
8
120Kns
Row Cycle Time
t_RC
12
-
AUTO REFRESH Row Cycle
Time
t_RFC
14
-
ACTIVE to READ,WRITE
delay
t_RCD
4
-
PRECHARGE command
period
t_RP
4
-
ACTIVE to READ with
AUTOPRECHARGE
t_RAP
4
-
command
ACTIVE bank A to ACTIVE
bank B command
t_RRD
2
-
Write recovery time
t_WR
15
-
Write data in to READ
command delay
t_WTR
2
-
Col. Address to Col. Address
delay
t_CCD
1
-
Average periodic refresh
interval
t_REFI
-
7.8
Write preamble
t_WPRE
0.25
-
Write postamble
t_WPST
0.4
0.6
DQS read preamble
t_RPRE
0.9
1.1
DQS read postamble
t_RPST
0.4
0.6
Clock to DQS write preamble
setup time
t_WPRES
0
-
Load Mode Register /
Extended Mode register
t_MRD
2
-
cycle time
Exit self refresh to READ
command
t_XSRD
200
-
Exit self refresh to
non-READ command
t_XSNR
75
-
Autoprecharge write
recovery+Precharge time
t_DAL
(t_WR/t_CK)
+
-
(t_RP/t_CK)
-6
min
t_CLmin or t_CHmin
t_HP-0.5
max
-
-
7
120Kns
10
-
12
-
3
-
3
-
3
-
2
-
15
-
2
-
1
-
-
7.8
0.25
-
0.4
0.6
0.9
1.1
0.4
0.6
0
-
1
-
200
-
75
-
(t_WR/t_CK)
+
-
(t_RP/t_CK)
Unit
ns
ns
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
ns
t_CK
t_CK
us
t_CK
t_CK
t_CK
t_CK
ns
t_CK
t_CK
ns
t_CK
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0
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