EN29F040 Datasheet, PDF (8/32 Pages) List of Unclassifed Manufacturers – 4 Megabit (512K x 8-bit) Flash Memory

EN29F040
Table 5. EN29F040 Command Definitions
Command
Sequence
Read/Reset
Read
Reset
Read/Reset
AutoSelect
Manufacturer ID
Write
Cycles
Req’d
1
1
4
4
AutoSelect Device ID 4
AutoSelect Sector
4
Protect Verify
Byte Program
4
Chip Erase
6
Sector Erase
6
Sector Erase Suspend 1
Sector Erase Resume 1
1^st
Write Cycle
Addr Data
RA RD
XXXh F0h
555h AAh
555h AAh
555h AAh
555h AAh
555h AAh
555h AAh
555h AAh
xxxh B0h
xxxh 30h
2^nd
Write Cycle
Addr Data
2AAh 55h
2AAh 55h
2AAh 55h
2AAh 55h
2AAh 55h
2AAh 55h
2AAh 55h
3^rd
Write Cycle
4^th
5^th
6^th
Write Cycle Write Cycle Write Cycle
Addr Data Addr Data Addr Data Addr Data
555h
555h
555h
555h
555h
555h
555h
F0h RA RD
90h
000h/
100h
7Fh/
1Ch
90h
001h/
101h
7Fh/
04h
90h
BA &
02h
00h/
01h
A0h PA PD
80h 555h AAh 2AAh 55h
80h 555h AAh 2AAh 55h
555h 10h
BA 30h
Notes:
RA = Read Address: address of the memory location to be read. This one is a read cycle.
RD = Read Data: data read from location RA during Read operation. This one is a read cycle.
PA = Program Address: address of the memory location to be programmed
PD = Program Data: data to be programmed at location PA
BA = Sector Address: address of the Sector to be erased. Address bits A17-A13 uniquely select any Sector.
Byte Programming Command
Programming the EN29F040 is performed on a byte-by-byte basis using a four bus-cycle operation
(two unlock write cycles followed by the Program Setup command and Program Data Write cycle).
When the program command is executed, no additional CPU controls or timings are necessary. An
internal timer terminates the program operation automatically. Address is latched on the falling edge
of CE or W E , whichever is last; data is latched on the rising edge of CE or W E , whichever is first.
The program operation is completed when EN29F040 returns the equivalent data to the programmed
location.
Programming status may be checked by sampling data on DQ7 (DATA polling) or on DQ6 (toggle
bit). Changing data from 0 to 1 requires an erase operation. When programming time limit is
exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations. The Command Definitions table shows the
address and data requirements for the chip erase command sequence.
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Rev. D, Issue Date: 2001/07/05
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