VMX1C1016 Datasheet, PDF (72/76 Pages) List of Unclassifed Manufacturers – Versa Mix 8051 Mixed-Signal MCU

VMX51C1016
The value written into the WDTREL register
defines the delay time of the watchdog timer as
follows:
WDT delay when the WDTREL bit 7 is cleared
WDT Delay = 24*[ 32768–(WDTREL(6:0) x 256)]
Fosc
WDT delay when the WDTREL bit 7 is set
WDT Delay = 384*[ 32768–(WDTREL(6:0) x 256)]
Fosc
The following table demonstrates WDT reload
values and their corresponding delay times:
Fosc
14.74MHz
14.74MHz
14.74MHz
WDTREL
00h
4Fh
CCh
WDT Delay
53.3ms
20.4ms
347ms
Note: The value present in the CLKDIVCTRL
register affects the watchdog timer delay time.
The above equations and examples assume that
the CLKDIVCTRL register content is 00h.
*** The Simple way ***
MOV
MOV
IEN0,#x1xxxxxxB
IEN1,#x1xxxxxxB
;DIRECT WRITE THAT SET BIT
;WDTR (x = 0 or 1)
;DIRECT WRITE THAT SET BIT
;WDTS (x = 0 or 1)
In the case where the program makes use of the
interrupts, it is recommended to deactivate the
interrupts before the watchdog refresh is
performed and reactivate them afterward.
b) Watchdog timer refresh example 2:
*** If Interrupts are used: ***
CLR
MOV
ORL
XCH
MOV
ORL
MOV
MOV
SETB
IEN0.7
A,IEN0
A,#01000000B
A,R1
A,IEN1
A,#01000000B
IEN0,R1
IEN1,A
IEN0.7
;Deactivate the interrupt
;Retrieve IEN0 content
;set the bit 6 (WDTR)
;Store IENO New Value
;Retrieve IEN1 content
;Set bit 6, (WDTS)
; Set WDTR BIT
;Set WDTS BIT
;Reactivate the Interrupts
Watchdog Timer Reset
To determine whether the reset condition was
caused by the watchdog timer, the state of the
WDTSTAT bit of the IP0 register should be
monitored. On a standard power-on reset
condition, this bit is cleared.
Starting the Watchdog Timer
To start the watchdog timer using the hardware
automatic start procedure, the WDTS (IEN1)
and WDTR (IEN0) bits must be set. The
watchdog will begin to run with default settings
i.e. all registers will be set to zero.
;*** Do a Watchdog Timer Refresh / Start sequence
SETB
IEN0.6
SETB
IEN1.6
;WDTS bit
;Set the WDTR bit first
;Then without delay set the
When the WDT registers enter the state 7FFFh,
the asynchronous signal, WDTS will become
active. This signal will set bit 6 in the IP0 register
and trigger a reset.
To prevent the watchdog timer from resetting the
VMX51C1016, reset it periodically by clearing
the WDTR and clear the WDTS bit immediately
afterward,.
As a security feature to prevent an inadvertent
clearing of the watchdog timer, no delay
(instruction) is allowed between the clearing of
the WDTR and WDTS bits.
a) Watchdog timer refresh example 1:
_________________________________________________________________________________________________
www.ramtron.com
page 72 of 76