VMX1C1016 Datasheet, PDF (63/76 Pages) List of Unclassifed Manufacturers – Versa Mix 8051 Mixed-Signal MCU

VMX51C1016
TABLE 112: (IEN1) INTERRUPT ENABLE 1 REGISTER -SFR E8H
7
T2EXIE
6
SWDT
5
ADCPCIE
4
MACOVIE
3
I2CIE
2
SPIRXOVIE
1
SPITEIE
0
reserved
Bit Mnemonic Function
7
T2EXIE
T2EX interrupt Enable
0 = Disable
1 = Enable
6
SWDT
Watch Dog timer start/refresh flag.
Set to activate/refresh the watchdog
timer. When directly set after setting
WDT, a watchdog timer refresh is
performed. Bit SWDT is reset.
5
ADCPCIE ADC and Port change interrupt
0 = Disable
1 = Enable
4
MACOVIE MULT/ACCU Overflow 32 bits
interrupt
0 = Disable
1 = Enable
3
I2CIE
I2C Interrupt
0 = Disable
1 = Enable
2
SPIRXOVIE SPI Rx avail + Overrun
0 = Disable
1 = Enable
1
SPITEIE
SPI Tx Empty interrupt
0 = Disable
1 = Enable
0
reserved
TABLE 113: (IEN2) INTERRUPT ENABLE 2 REGISTER - SFR 9AH
7
6
5
4
3
2
1
-
-
-
-
-
-
-
0
S1IE
Bit Mnemonic Function
7-1
-
-
0
S1IE
UART 1 Interrupt
0 = Disable UART 1 Interrupt
1 = Enable UART 1 Interrupt
Timer 2 Compare Mode Impact on
Interrupts
The SPI RX (and RXOV), I²C, MULT/ACCU and
ADC interrupts are shared with the four Timer 2
compare and capture unit interrupts.
When the compare and capture units of Timer 2
are configured in compare mode via the CCEN
register, the compare and capture unit takes
control of one interrupt vector as shown in the
next figure.
FIGURE 43: COMPARE CAPTURE INTERRUPT STRUCUTRE
COMPINT0
Interrupt
SPI Rx &
RxOV INT
1
Interrupt Vector
0053h
0
CCEN(1,0) = 1,0
COMPINT1
Interrupt
1
I2C INT
0
Interrupt Vector
005Bh
CCEN(3,2) = 1,0
COMPINT2
Interrupt
1
MAC
Overflow INT
0
CCEN(5,4) = 1,0
COMPINT3
Interrupt
1
ADC & Port
Change INT
0
CCEN(7,6) = 1,0
Interrupt Vector
0063h
Interrupt Vector
006Bh
The impact of this is that the corresponding
peripheral interrupt, if enabled, will be blocked.
The output signal from the comparison module
will be routed to the interrupt system and the
control lines will be dedicated to the compare
and capture unit.
This interrupt control “take over” is specific to
each individual compare and capture unit. For
example if Compare and Capture Unit 2 is
configured to generate a PWM signal on P1.2,
the MULT/ACCU overflow interrupt, if enabled,
will be dedicated to Compare and Capture Unit 2
and the SPI, I²C and ADC interrupts won’t be
affected.
_________________________________________________________________________________________________
www.ramtron.com
page 63 of 76