NT6880 Datasheet, PDF (7/13 Pages) List of Unclassifed Manufacturers – Keyboard Controller

NT6880
10. LED PORT
There are 3 LED direct sink pins which require no external serial resistors. The address is mapped to address $00C9.
Addr. Register Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$00C9
LED
-
-
-
-
-
LED2 LED1 LED0
(W)
WREN
DB
RST
L
Q
D _SD
LED [ 0 ]
WREN
DB
RST
L
Q
D _SD
V DD
LED [ 1:2 ]
Figure 10.1. LED0 Port Structure
Figure 10.2. LED1, LED2 Port Structures
11. Watch-Dog Timer (WDT)
NT6880 implements a watch-dog timer, which protects programs against system standstill. The clock of the watch-dog
timer is derived from the on-chip RC oscillator. The watch-dog timer interval is about 0.175 of a second. The timer must be
cleared within every 0.175 second during normal operation; otherwise, it will overflow and cause a system reset. The
watch-dog timer is cleared and enabled after a system reset. It cannot be disabled by the software. A user can clear the
watch-dog timer by writing #55H to CLRWDT ($00CAH) register.
For example:
LDA
STA
#$55
$00CA
Addr. Register Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$00CA CLRWDT
0
1
0
1
0
1
0
1
(W)
12. Low Voltage Reset (LVR) Circuit
The NT6880 will check on the voltage level of power supply. When the voltage level of power supply is below a threshold of
3.0V (Typical), the LVRC will issue a reset output to the chip until the power voltage level is above the threshold voltage of
3.0V (Typical) again. As soon as the power voltage arises to 3.0V (Typical), the entire chip will be reset for about 150ms.
13. RESET
NT6880 can also be externally reset via the RESET pin. A reset is initiated when the signal at the RESET pin is held Low
for at least 10 system clocks. As soon as the RESET signal goes high, the NT6880 begins to be reset for about 150ms.
The following shows the definition of the RESET input low pulse width.
V DD
V DD
20%V DD
Trstb
20%V DD
7