NT6880 Datasheet, PDF (5/13 Pages) List of Unclassifed Manufacturers – Keyboard Controller

6. Timing Generator
This block generates the system timing and control
signal supplied to the CPU and on-chip peripherals.
There are two types of system clock sources: built-in RC
oscillator or external ceramic resonator. Both are mask
optional and generate a 4MHz system clock. They also
generate 2MHz for the CPU, and 1 MHz for base timer.
NT6880
The following table provides the relationship between
external resistor and RC OSC frequency. (for reference
only)
External Resistor
(KΩ )
39
43
47
56
RC OSC Frequency (MHz)
4.7
4.44
4
3.68
7. Base Timer (BT)
The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by CPU. After reset,
the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any time.
When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a timer
interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and
begin counting at 00H. The timer interval can be programmed from 1 - 256 µsec. The base timer can be enabled by writing
a '0' to ' ENBT ' in the TCON (Timer Control) register. The ENBT is a level trigger.
Base timer structure:
8-Bit timer
1µs
BT7 BT6 BT5 BT4 BT2 BT2 BT1 BT0
TMRINT
BT pre-load data:
Addr.
Bit
$00C0 BT
Timer Control Register:
7
6
5
4
3
2
1
BT7 BT6 BT5 BT4 BT3 BT2 BT1
0
R/W
BT0 (W)
$00C1 TCON
-
-
-
-
-
-
-
ENBT ^(W)
8. Interrupt Controller
When a BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by the
software. Once set by an interrupt source, it remains High unless cleared by writing '1' to the corresponding bit in
CLRIRQX ($00C2H). This register is cleared to '0' on initialization by a system reset.
When an interrupt occurs, the CPU will jump to $FFFEH & $FFFFH to execute an interrupt service routine. When the
BASE TIMER interrupt occurs and enters an interrupt service routine, the IRQTMR flag must be cleared by the software.
Interrupt Control Register:
Addr.
$00C2
Bit
7
6
5
4
3
2
1
0
R/W
CLRIRQX -
-
-
-
-
-
- CLRIRQTMR (W)
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