CS18LV20483 Datasheet, PDF (7/16 Pages) List of Unclassifed Manufacturers – High Speec Super Low Power SRAM

High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
LOW Vcc DATA RETENTION WAVEFORM 1 ( /CE1 Controlled )
LOW Vcc DATA RETENTION WAVEFORM 2 ( CE2
Controlled )
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
Input Rise and Fall Times
5ns
Input and Output Timing
Reference Level
Output Load
0.5Vcc
See FIGURE 1A
and 1B
KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
OUTPUTS
MUST BE STEADY MUST BE STEADY
MAY CHANGE
FROM H TO L
WILL BE CHANGE FROM H
TO L
MAY CHANGE
FROM L TO H
WILL BE CHANGE FROM L
TO H
DON’T CARE ANY
CHANGE
PERMITTED
CHANGE STATE
UNKNOWN
DOES NOT APPLY
CENTER LINE IS HIGH
IMPEDANCE OFF STATE
7
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.