CS18LV20483 Datasheet, PDF (4/16 Pages) List of Unclassifed Manufacturers – High Speec Super Low Power SRAM

High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
PIN DESCRIPTIONS
Name
A0 – A17
/CE1, CE2
/WE
/OE
DQ0~DQ7
Vcc
Gnd
NC
Type
Function
Input
Input
Input
Input
I/O
Power
Power
Address inputs for selecting one of the 262,144 x 8 bit words in the RAM
/CE1 is active LOW and CE2 is active HIGH. Both chip enables must be
active when data read from or write to the device. If either chip enable is
not active, the device is deselected and in a standby power down mode.
The DQ pins will be in high impedance state when the device is
deselected.
The Write enable input is active LOW. It controls read and write
operations. With the chip selected, when /WE is HIGH and /OE is LOW,
output data will be present on the DQ pins, when /WE is LOW, the data
present on the DQ pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active
while the chip is selected and the write enable is inactive, data will be
present on the DQ pins and they will be enabled. The DQ pins will be in
the high impedance state when /OE is inactive.
These 8 bi-directional ports are used to read data from or write data into
the RAM.
Power Supply
Ground
No connection
TRUTH TABLE
MODE
/CE1 CE2 /WE
/OE
H
X
X
X
Standby
X
L
X
L
Output
H
H
L
H
Disabled
Read
L
H
H
L
Write
L
H
L
X
DQ0~7 Vcc Current
High Z
I_CCSB, I_CCSB1
High Z
I_CC
D_OUT
I_CC
D_IN
I_CC
4
Rev. 1.0
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