CCD30-11 Datasheet, PDF (7/9 Pages) List of Unclassifed Manufacturers – Open Electrode High Performance CCD Sensor

DETAIL OF OUTPUT CLOCKING
R11
R12
T_r
t_or
R13
t_wx
1R
OS
RESET FEEDTHROUGH
LINE OUTPUT FORMAT
8 BLANK
t_dx
OUTPUT
VALID
7133A
SIGNAL
OUTPUT
8 BLANK
7130A
1024 ACTIVE OUTPUTS
CLOCK TIMING REQUIREMENTS
Symbol
T_i
t_wi
t_ri
t_fi
t_oi
t_li
t_dir
t_dri
T_r
t_rr
t_fr
t_or
t_wx
t_rx, t_fx
t_dx
Description
Image clock period
Image clock pulse width
Image clock pulse rise time (10 to 90%)
Image clock pulse fall time (10 to 90%)
Image clock pulse overlap
Image clock pulse, two phase low
Delay time, I1 stop to R1 start
Delay time, R1 stop to I1 start
Output register clock cycle period
Clock pulse rise time (10 to 90%)
Clock pulse fall time (10 to 90%)
Clock pulse overlap
Reset pulse width
Reset pulse rise and fall times
Delay time, 1R low to R13 low
Min
50
25
5
t_ri
3
2
3
1
200
50
t_rr
20
30
20
30
Typical
Max
90
see note 10
ms
45
see note 10
ms
20
0.5t_oi
ms
20
0.5t_oi
ms
10
0.2T_i
ms
10
0.2T_i
ms
10
see note 10
ms
2
see note 10
ms
see note 11
see note 10
ns
0.1T_r
0.1T_r
0.5t_rr
0.1T_r
0.5t_rr
0.5T_r
0.3T_r
ns
0.3T_r
ns
0.1T_r
ns
0.2T_r
ns
0.2T_r
ns
0.8T_r
ns
NOTES
10. No maximum other than that necessary to achieve an acceptable dark signal at the longer readout times.
11. As set by the readout period.
# e2v technologies
100008, page 7