U63764 Datasheet, PDF (6/14 Pages) List of Unclassifed Manufacturers – CapStore 8K x 8 nvSRAM

U63764
Write Cycle #1: W-controlled^j
Ai
E
W
DQi
Input
DQi
Output
t_{cW (12)}
Address Valid
t_{su(E) (17)}
t_h(A) (21)
t_su(A)
(15)
t_{su(A-WH) (16)}
t_{w(W) (13)}
t_{su(D) (19)}
t_{h(D) (20)}
Input Data Valid
t_{dis(W) (22)}
t_{en(W) (23)}
Previous Data
High Impedance
Write Cycle #2: E-controlled^j
Ai
E
W
DQi
Input
DQi
Output
t_su(A) (15)
t_cW (12)
Address Valid
t_{w(E) (18)}
t_{h(A) (21)}
t_su(W) (14)
t_{su(D) (19)}
t_{h(D) (20)}
Input Data Valid
High Impedance
undefined
L- to H-level
H- to L-level
i: If W is low and when E goes low, the outputs remain in the high impedance state.
j: E or W must be V_IH during address transition.
STK Control #ML0055
6
Rev 1.0
March 31, 2006