U63764 Datasheet, PDF (12/14 Pages) List of Unclassifed Manufacturers – CapStore 8K x 8 nvSRAM

U63764
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
valid. After the t_STORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation. When V_CC < V_SWITCH all software STORE
operations will be inhibited.
Any SRAM WRITE cycles requested after the V_CC pin
drops below V_SWITCH will be inhibited.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1. Read addresses 0000 (hex) Valid READ
2. Read addresses 1555 (hex) Valid READ
3. Read addresses 0AAA (hex) Valid READ
4. Read addresses 1FFF (hex) Valid READ
5. Read addresses 10F0 (hex) Valid READ
6. Read addresses 0F0E (hex) Initiate RECALL
Cycle
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. After
t_d(E)R cycle time the SRAM will once again be ready for
READ and WRITE operations.The RECALL operation
in no way alters the data in the EEPROM cells. The
nonvolatile data can be recalled an unlimited number of
times.
Low Average Active Power
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the V_CC level
STK Control #ML0055 12
Rev 1.0
March 31, 2006