SA9904B Datasheet, PDF (6/12 Pages) List of Unclassifed Manufacturers – Three Phase Power / Energy IC with SPI Interface

SA9904B
sames
and the SCK pin of the SA9904B. The DI and DO pins are the
serial data input and output pins for the SA9904B, respectively.
Register Access
Table 1 lists the various register addresses. The SA9904B
contains nine 24 bit- registers representing the active energy,
reactive energy and the mains voltage for each phase. A tenth
24 bit register represents the mains frequency for any valid
phase. To remain compatible with the SA9604A three
addresses have been included. Any of the three addresses can
be used to access the frequency register.
ID Register
1 Active Phase 1
2 Reactive Phase 1
3 Voltage Phase 1
4 Frequency
5 Active Phase 2
6 Reactive Phase 2
7 Voltage Phase 2
8 Frequency
9 Active Phase 3
10 Reactive Phase 3
11 Voltage Phase 3
12 Frequency
Header
bits ^{A5 A4 A3 A2 A1 A0}
110XX0 000
110XX0 001
110XX0 010
110XX0 011
110XX0 100
110XX0 101
110XX0 110
110XX0 111
110XX1 000
110XX1 001
110XX1 010
110XX1 011
Table 1: Register address
The 9 bits needed for register addressing can be padded with
leading zeros when the micro-controller requires a 8 bit SPI
word length. The following sequence is valid:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 1 0 A5 A4 A3A2A1 A0
Data format
Figure 8 shows the SPI waveforms and figure 9 the timing
information. After the least significant digit of the address has
been entered on the rising edge of SCK, the output DO goes
low with the falling edge of SCK. Each subsequent falling edge
transition on the SCK pin will validate the next data bit on the
DO pin.
The content of each register consists of 24 bits of data. The
MSB is shifted out first.
SCK
t3
t4
DI
t2
t5
DO
t1
CS
DR-01545
The header bits 110 (0x06) must precede the 6-bit address of the
register being accessed. When CS is HIGH, data on pin DI is
clocked into the SA9904B on the rising edge of SCK. Figure 8
shows the data clocked into DI comprising of 1 1 0 A5 A4 A3 A2
A1 A0. Address locations A5 and A4 are included for
compatibility with future developments.
Registers may be read individually and in any order. After a
register has been read, the contents of the next register value
will be shifted out on the DO pin with every SCK clock cycle. Data
output on DO will continue until CS is inactive.
Parameter Description
Min Max
t1
SCK rising edge to DO valid 625ns 1.160µs
t3
SCK min high time
625ns
t4
SCK min low time
625ns
t2
Setup time for DI and CS
before the rising edge of SCK 20ns
t5
DI hold time
625ns
Figure 9: SPI Timing diagrams with timing information
SCK
CS
Read command
Register address
DI
1
1
0
A5
A4
A3
A2
A1
A0
DO
Dr-01647
Register Data
0
D23
D22
D21
Figure 8: SPI waveforms
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Next data register
D1
D0
D23
D22
High impedance
D1
D0