SA9904B Datasheet, PDF (5/12 Pages) List of Unclassifed Manufacturers – Three Phase Power / Energy IC with SPI Interface

SA9904B
sames
Where:
IL = Line current or if a CT is used IL = Line current / CT ratio
Rsh = Shunt resistor or CT termination resistor.
Rsh should be less than the resistance of the CT's secondary
winding.
Voltage Sense Input (IVP1, IVP2, IVP3)
Figure 6 shows the voltage sense (IVP) input configuration for
one phase. The exact circuit is duplicated for the other two
phases. The current into the voltage sense inputs (virtual
ground) should be set to 14µARMS at rated voltage conditions.
The voltage sense inputs saturate at an input current of ±25µA
peak.
Ch1 Voltage
R16
R19
R22
14VRMS
C5
R8
14µARMS
IVP1
Neutral
R13
Dr-01645
GND
GND
Figure 6: Voltage sense input configuration
The individual mains voltages are divided down to 14VRMS per
phase. The resistor R8 sets the current for the voltage sense
input. The voltage divider is calculated for a voltage drop of 14V.
With a phase voltage of 230V the equation for the voltage divider
is:
RA = R16 + R19 + R22
RB = R8 || R13
Combining the two equations gives:
(RA + RB) / 230V = RB / 14V
A 24K resistor is chosen for R13 and a 1M resistor for R8.
Substituting these values results in:
RB = 23.44K
RA = RB x (230V / 14V-1)
RA = 361.6K
Resistor values for R16, R19 and R22 is chosen to be 120K
each.
The capacitor C5 is used to compensate for any phase shift
between the voltage sense and current sense input caused by
the current transformer. As an example to compensate for a
phase shift of 0.18 degrees the capacitor value is calculated as
follows:
C = 1 / (2 x p x Mains frequency x R5 x tan (Phase shift angle))
C = 1 / (2 x p x 50Hz x 1MW x tan (0.18 degrees))
C = 1.013µF
Reference Voltage (VREF)
The VREF pin is the reference for the bias resistor. With a bias
resistor of 47kW connected to Vss optimum conditions are set.
Serial Clock (SCK)
The SCK pin is used to synchronize data interchange between
the micro controller and the SA9904B. The clock signal on this
pin is generated by the micro controller and determines the
data transfer rate of the DO and DI pins.
Serial Data In (DI)
The DI pin is the serial data input pin for the SA9904B. Data will
be input at a rate determined by the Serial Clock (SCK). Data
will be accepted only during an active chip select (CS).
Chip Select (CS)
The CS input is used to address the SA9904B. An active high
on this pin enables the SA9904B to initiate data exchange.
OUTPUT SIGNALS
Serial Data Out (DO)
The DO pin is the serial data output pin for the SA9904B. The
Serial Clock (SCK) determines the data output rate. Data is
only transferred during on active chip select (CS). This output
is tri-state when CS is low.
Mains Voltage sense zero crossover (F50)
The F50 output generates a signal, which follows the mains
voltage zero crossings, see figure 7. This output generates a
pulse on the rising edge of the mains voltage zero crossing
point. Internal logic ensures that this signal is generated from a
valid phase. Should all three phase be missing but power still
applied to the SA9904B this output will generate a constant
54Hz signal. The micro controller can use the F50 to extract
mains timing.
Phase Voltage
F50
Dr-01646
1ms to 2ms
+5V
0V (Vss)
1ms to 2ms
Figure 7: Mains voltage zero crossover
SPI - INTERFACE
Description
A serial peripheral interface bus (SPI) is a synchronous bus
used for data transfers between a micro controller and the
SA9904B. The pins DO (Serial Data Out), DI (Serial Data In),
CS (Chip Select), and SCK (Serial Clock) are used in the bus
implementation. The SA9904B is the slave device with the
micro controller being bus master. The CS input initiates and
terminates data transfers. A SCK signal (generated by the
micro controller) strobes data between the micro-controller
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