OZ6912 Datasheet, PDF (6/14 Pages) List of Unclassifed Manufacturers – Single-Slot ACPI CardBus Controller

OZ6912
Pin Name
PAR
PCI_CLK
RST#
GNT#
REQ#
Description
Parity: This pin generates PCI parity and ensures
even parity across AD[31:0] and C/BE[3:0]#.
During the address phase, PAR is valid after one
clock. With data phases, PAR is stable one clock
after a write or read transaction.
PCI Clock: This input provides timing for all
transactions on the PCI bus to and from the
OZ6912. All PCI bus signals, except RST#, are
sampled and driven on the rising edge of
PCI_CLK. This input can be operated at
frequencies from 0 to 33 MHz.
Device Reset: This input is used to initialize all
registers and internal logic to their reset states
and place most OZ6912 pins in a HIGH-
impedance state.
Grant: This signal indicates that access to the bus
has been granted.
Request: This signal indicates to the arbiter that
the OZ6912 requests use of the bus.
Pin Number
LQFP
BGA
36
M2
21
H1
20
G4
2
B1
1
A1
Input Type
TTL I/O
Power
Rail
PCI_Vcc
Drive
PCI
Spec
-
I
PCI_Vcc
-
-
I
AUX_Vcc
-
TTL
I
- TO
PCI_Vcc
PCI_Vcc
PCI
Spec
PCI
Spec
Power Control and General Interface Pins
Pin Name
RI_OUT/
PME#
Description
Ring Indicate Out: This pin is Ring Indicate
when the following occurs while O2 Mode Control
B Register (index 2Eh) bit 7 is set to 1:
1) Power Control (Index+02h) bit 7 set to 1
2) Interrupt and General Control (Index+03h)
bit 7 set to 1
3) PCI O2Micro Control 2 (Offset: D4h) bit X =
0
Pin Number
LQFP
BGA
59
L8
SPKR_OUT#
MF[6:0]
Power Management Event: A power
management event is the process by which the
OZ6912 can request a change of its power
consumption state. Usually, a PME occurs
during a request to change from a power saving
state to the fully operational state.
Speaker Output: This output can be used to
support PC Card audio output. See O2 Mode E
Register (Index + 3Eh), bit 1.
Multifunction Terminal [6:0]: See PCI
Multifunction MUX Register (Offset:08h).
62
60-61, 64-65,
67-69
SUSPEND# Suspend: This signal is used to protect the
70
internal registers from clearing when the PCI
RST# signal is asserted. When low, this signal is
used to mask the PCI RESET during suspend.
This pin can be used during suspend to prevent
controller reset.
G_RST#
Global_Reset#: This signal can be connected to
66
either PCI reset or ACPI reset depending on
system implementation. If the D3 cold state is
implemented, this signal should be connected to
the ACPI reset, otherwise, connect to PCI reset.
This signal can reset the PME content under the
D3 cold state if AUX_VCC is provided.
M9
K8, N9, K9,
N10, L10,
N11, M11
L11
M10
Input Type
-
TO
Power
Rail
Aux_Vcc
Drive
4mA
TTL I/O Aux_Vcc 6mA
TTL I/O Aux_Vcc 6mA
TTL
I
Aux_Vcc
-
TTL
I
Aux_Vcc
-
OZ6912-SF-1.5
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