HX6656 Datasheet, PDF (6/12 Pages) List of Unclassifed Manufacturers – 32K x 8 ROM-SOI

HX6656
READ CYCLE AC TIMING CHARACTERISTICS (1)
Symbol
Parameter
TAVAVR Address Read Cycle Time
TAVQV Address Access Time
TAXQX Address Change to Output Invalid Time
TSLQV Chip Select Access Time
TSLQX Chip Select Output Enable Time
TSHQZ Chip Select Output Disable Time
TEHQV Chip Enable Access Time (4)
TEHQX Chip Enable Output Enable Time (4)
TELQZ Chip Enable Output Disable Time (4)
TGLQV Output Enable Access Time
TGLQX Output Enable Output Enable Time
TGHQZ Output Enable Output Disable Time
Typical
(2)
Worst Case (3)
-55 to 125°C
Min
Max
25
25
3
25
5
10
25
5
10
9
0
9
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading C_L >50 pF, or equivalent
capacitive output loading C_L=5 pF for TSHQZ, TELQZ TGHQZ. For C_L >50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55°C to +125°C, post total dose at 25°C.
(4) Chip Enable (CE) pin not available on 28-lead FP or DIP.
ADDRESS
NCS
DATA OUT
CE
NOE
TAVAVR
TAVQV
TSLQV
TSLQX
HIGH
IMPEDANCE
TEHQX
TEHQV
TGLQX
TGLQV
TAXQX
DATA VALID
TSHQZ
TELQZ
TGHQZ
6