GO7007 Datasheet, PDF (6/10 Pages) List of Unclassifed Manufacturers – WIS GO7007 Single-Chip Streaming Media Encoder

38
AD6
39
AD7
40
AD8
41
AD9
42
AD10
43
VSS_IO
44
VDD_IO
45
SDRAM_DQ7
46
VDD_CORE
47
VSS_CORE
48
SDRAM_DQ6
49
SDRAM_DQ5
50
SDRAM_DQ4
51
SDRAM_DQ3
52
VSS_IO
90
SDRAM_DQ31
91
SDRAM_DQ30
92
SDRAM_DQ29
93
SDRAM_DQ28
94
VSS_IO
95
VDD_IO
96
SDRAM_DQ27
97
SDRAM_DQ26
98
VDD_CORE
99
VSS_CORE
100 SDRAM_DQ25
101 VSS_IO
102 VDD_IO
103 SDRAM_DQ24
104 SDRAM_DQ23
142 USB+
143 USB-
144 VSS_USB
145 USB_CLK
146 PDATA0
147 PDATA1
148 PDATA2
149 PDATA3
150 VDD_CORE
151 VSS_CORE
152 PDATA4
153 PDATA5
154 PDATA6
155 PDATA7
156 HREF
194 VDD_IO
195 MXI
196 MXO
197 SYNC_HPI
198 DBG_INT
199 MCLK
200 USBRST_EN
201 RESET#
202 VDD_CORE
203 VSS_CORE
204 DEBUG_MODE
205 BIST_FAIL
206 BIST_DONE
207 BIST_RESET
208 BIST_RUN
Table 0-2 Pin Description
Symbol
PLL Pins
AVDD_MPLL
Pin #
1, 3
VSS_MPLL
DVDD_MPLL
2, 4, 5
6
MPLL_BP
8
UPLL_BP
9
MXI
195
MXO
196
MCLK
199
Built-In Self Test Pins
TEST_EN
10
Pin Type
Description
Note
Supply
Supply
Supply
Input
Input
Input
Output
Input
1.8V Analog power supply for Master clock
PLL
Ground for Master clock PLL
1.8V Digital power supply for Master clock
PLL
Master clock PLL Bypass. When pin is tied
to ground, master clock is generated by
internal PLL locked to MXI. Otherwise,
MCLK is used as master clock input.
USB clock PLL Bypass. When pin is tied to ₁
ground, USB clock is generated by
internal PLL locked to MXI. Otherwise,
USB_CLK is used as USB clock input.
Oscillator Input
Usually connected to the crystal
Use this Master Clock input pin when
Master clock PLL is bypassed.
Input
Test Enable. Reserved for manufacturers’
use. Connect pin to ground under normal
operation.
PAGE 6