COM20051 Datasheet, PDF (59/82 Pages) List of Unclassifed Manufacturers – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

Upon entering the ISR, the status register is read
and the TMA bit is checked. If the TMA bit is not
set, then the action as described above is taken.
If TMA is good then the interrupt is cleared and
either bit 6 or bit 5 of the TX_PEND_REG is
cleared depending on the number of
transmissions pending. The configuration
register is then read and the Command Chaining
enable bit is checked. If Command Chaining is
enabled, then bit 4 of TX_PEND is set, otherwise
it is cleared. A series of case statements are
then executed which read the TX_PEND_REG
and look for a set bit. If a bit is set in the lower
nibble, it signifies that the ARCNET RAM has
been loaded with data and that page is ready to
be transmitted. Software should be written so
that an external routine will copy transmit data
into the ARCNET RAM. This will speed up the
ISR. Bits 5 and 6 are checked to see that the
pipeline is not completely filled. If they are both
set, then the routine is exited. If either one of the
bits
is
reset,
then
the
pending bit in TX_PEND_REG is reset, bit 5 or
6 is set, and an Enable to Transmit command is
given to the page corresponding to the bit
position in TX_PEND_REG.
Up to two transmit commands can be given
within the ISR at any given time. If no
transmissions are pending, then the routine is
exited without any new transmissions.
Initiating Transmissions
The Transmit Service routine can only execute
after a transmission occurs. Therefore, initial
transmit commands must originate from routines
external to the Transmit Interrupt service
routine. The Transmit ISR can only transmit
packets if and only if packets are pending
transmission upon entry into the routine.
Normally this is not the case, thus the
programmer must take care to monitor and
update the TX_PEND_REG for each
transmission.
BIT 7
NOT
USED
BIT 6
BIT 5
TX CMD #2 TX CMD #1
ISSUED ISSUED
TX_PEND_REG
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NOT
USED
TX PEND. TX PEND. TX PEND. TX PEND.
IN
IN
IN
IN
BUFFER 4 BUFFER 3 BUFFER 2 BUFFER 1
BIT 7
BIT 6
BIT 5
RAM_BUF_REG
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NOT
USED
NOT
USED
NOT
USED
NOT
USED
NOT
USED
NOT
USED
RX BUF RX BUF
2
1
BIT 7
BIT 6
BIT 5
RX_PAGE_REG
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RECEIVE COMMAND PAGE #2
RECEIVE COMMAND PAGE #1
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