COM20051 Datasheet, PDF (27/82 Pages) List of Unclassifed Manufacturers – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

Interrupt Routing Register (Location +09HEX)
The Interrupt Routing Register (IRR) routes the
interrupt generated by the ARCNET core to the
appropriate 80C32 interrupt input (INT0 or INT1)
or to one of the eight general purpose digital I/O
ports (P1.0-1.7) of the 80C32. The interrupt
routing operates on a priority driven scheme
where if two bits are enabled the highest priority
always wins. INT0 has highest priority followed
by INT1 then EXT. The nINT0 and nINT1 bits
route the interrupt signal to either the nINT0 or
nINT1 pin of the 80C32. The 80C32 nINT1 and
nINT0 inputs are wire ANDed with the routed
interrupt. This allows the 80C32's interrupts to be
used for more than one source. If many
interrupts are being used in the system, the
COM20051 supports the use of an external
interrupt controller to arbitrate simultaneous
interrupts. External interrupt controllers are
supported by programming the EXT bit of the
IRR. This will cause the interrupt signal to be
present on one of the Port 1 pins as programmed
by Bits 3 - 5.
The 5 Mbps bit programs the ARCNET core to
operate at a 5 Mbps data rate. The 5 Mbps bit
causes the clock to the ARCNET core to double
its frequency from 20MHz to 40MHz. 5 Mbps
operation requires the SLOWARB bit of the
SETUP register to be set. Failure to set the
SLOWARB bit may result in errors when
accessing the ARCNET buffer RAM.
Table 6 - Interrupt Routing Register
BIT
BIT NAME
SYMBOL
DESCRIPTION
6
5 Mbps Enable
5MBPS Causes the ARCNET core to operate at a 5 Mbps
data rate. Defaults to 0.
3-5 Port 1 Bit
Assignment
DEC1 - 3
Selects one of the eight Port 1 bits to output the
interrupt on.
000 - P1.0
001 - P1.1
010 - P1.2
011 - P1.3
100 - P1.4
101 - P1.5
110 - P1.6
111 - P1.7
Defaults to 000 (P1.0).
2
External Interrupt EXT
Enable
1
Interrupt 1
Enable.
INT1
0
Interrupt 0
Enable.
INT0
Enables routing of the ARCNET interrupt onto on
the Port 1 pins. Defaults to 0.
Enables wire Oring of the ARCNET interrupt with
the INT1 pin. Defaults to 0.
Enables wire ORing if the ARCNET interrupt with
the INT0 pin. Defaults to 0.
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