COM20051 Datasheet, PDF (58/82 Pages) List of Unclassifed Manufacturers – Integrated Microcontroller and ARCNET (ANSI 878.1) Interface

Receive Interrupt
A basic Receive service routine is shown in the
flowchart of Figure 19. The basic concept of the
service routine is not to process the packet data
but to remove the packet from the ARCNET
buffer and free the buffer for another reception.
This method will minimize the number of missed
packets due to unavailable buffers.
The Receiver Interrupt Service Routine
(RX_ISR) will handle one reception at a time and
enable another receive command upon exiting
the service routine. Received data is stored in
one of four buffers in external RAM. Several
variables are kept in order to facilitate
processing. RAM_BUF_REG is a byte wide, bit
mapped software register which shows which
external buffers are empty so that new data can
be copied. RX_PAGE_REG is a byte wide
register in which the lower nibble contains the
ARCNET buffer RAM page address in which the
latest reception can be found. The upper nibble
contains the page address in which the next
received is to be stored. This register allows the
service routine to track from which page the most
current data can be found when back to back
Enable to Receive commands are issued. MI-
N_RX_PAGE and MAX_RX_PAGE are two
constants that contain the page address
boundaries for the ARCNET memory. If it is
desired to allow more RAM for receptions and
less RAM for transmissions then these constants
must be changed accordingly.
Upon entering the RX_ISR the RX_PAGE_REG
is read. The lower three bits are masked off and
stored as the page address. RAM_BUF_REG is
then read and the first free buffer found is used
to store the packet. Once the data has been
copied, the RAM_BUF_REG is checked to make
sure that at least one buffer is empty before
issuing another receive command. If no buffers
are available, the interrupt is cleared and a new
command is issued, thus discarding the received
packet. This is done so that all receptions are
handled. If it is found that receptions are being
missed then more buffering on the CPU side is
necessary. If a free buffer exists, the second
receive command page is then checked to see if
the maximum page address has been reached. If
the page address is at its maximum value, then
the page address is set to the minimum page
address, otherwise the page address is
incremented to next page. The Enable to
Receive command string is then generated from
the page address. RX_PAGE_REG is updated
to make the second receive command the first
command and the new command will be the
second command. The actual command is then
issued. The Clear Receive Interrupt command is
then issued and the routine is exited.
Transmit Interrupt Servicing
The Transmit ISR (TX_ISR) services interrupts
caused by the TA bit being set. The routine will
first check the TMA bit to see if the last
transmission has been received error free. If
TMA is good then another transmission occurs. If
TMA is bad then the last transmission is sent
again and the ISR is exited. Limits can be
imposed on the number of re-tries before
aborting.
Several variables are kept in order to simplify
servicing of the Transmit interrupt.
TX_PEND_REG is a byte wide, bit mapped
register that conveys information about whether
a packet needs to be transmitted and where it is
located in the ARCNET RAM. The lower nibble
of the register tells the ISR from which external
RAM page the transmit data is to come. Bits 5
and 6 are status bits telling the ISR how many
transmit commands are in the Command
Chaining pipeline. To identify from which
ARCNET buffer page the last transmission
originated, a variable called LAST_TX is used
that contains the page number used in the last
Enable to Transmit command. LAST_TX is used
to re-transmit data when a bad TMA bit is found.
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