LM3S6965_0711 Datasheet, PDF (544/578 Pages) List of Unclassifed Manufacturers – Microcontroller

Electrical Characteristics
23.2.7
b. IEEE 802.3 frequency tolerance ±50 ppm.
Hibernation Module
The Hibernation Module requires special system implementation considerations since it is intended
to power-down all other sections of its host device. The system power-supply distribution and
interfaces of the system must be driven to 0 V_DC or powered down with the same regulator controlled
by HIB.
The regulators controlled by HIB are expected to have a settling time of 250 μs or less.
Table 23-22. Hibernation Module Characteristics
Parameter No Parameter
Parameter Name
Min Nom Max Unit
H1
t_{HIB_LOW} Internal 32.768 KHz clock reference rising edge to /HIB asserted - 200 - μs
H2
t_{HIB_HIGH} Internal 32.768 KHz clock reference rising edge to /HIB deasserted - 30 - μs
H3
t_{WAKE_ASSERT} /WAKE assertion time
62 - - μs
H4
t_WAKETOHIB /WAKE assert to /HIB desassert
H5
t_{XOSC_SETTLE} XOSC settling time^a
62 - 124 μs
20 - - ms
H6
t_{HIB_REG_WRITE} Time for a write to non-volatile registers in HIB module to complete 92 - - μs
H7
t_{HIB_TO_VDD} HIB deassert to VDD and VDD25 at minimum operational level
- - 250 μs
a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care
must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance).
Figure 23-4. Hibernation Module Timing
32.768 KHz
(internal)
H1
H2
/HIB
H4
/WAKE
H3
23.2.8
Synchronous Serial Interface (SSI)
Table 23-23. SSI Characteristics
Parameter No. Parameter Parameter Name
Min Nom Max
Unit
S1
t_{clk_per} SSIClk cycle time
2 - 65024 system clocks
S2
t_{clk_high} SSIClk high time
- 1/2 -
t clk_per
S3
t_{clk_low} SSIClk low time
- 1/2 -
t clk_per
S4
t_clkrf SSIClk rise/fall time
- 7.4 26
ns
S5
t_DMd Data from master valid delay time 0 - 20
ns
S6
t_DMs Data from master setup time
20 -
-
ns
S7
t_DMh Data from master hold time
40 -
-
ns
544
November 30, 2007
Preliminary