LM3S6965_0711 Datasheet, PDF (524/578 Pages) List of Unclassifed Manufacturers – Microcontroller

Signal Tables
Pin Name
CMOD0
CMOD1
Fault
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDA
GNDA
GNDPHY
GNDPHY
GNDPHY
GNDPHY
HIB
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
IDX0
IDX1
LDO
LED0
Pin Number
65
76
99
9
15
21
33
39
45
54
57
63
69
82
87
94
4
97
41
42
85
86
51
70
71
34
35
10
61
7
59
Pin Type
I/O
I/O
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
I
I
I
O
I/O
I/O
I/O
I/O
I
I
-
O
Buffer Type Description
TTL
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
TTL
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
TTL
PWM Fault
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power Ground reference for logic and I/O pins.
Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
Power
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
TTL
GND of the Ethernet PHY
TTL
GND of the Ethernet PHY
TTL
GND of the Ethernet PHY
TTL
GND of the Ethernet PHY
TTL
An output that indicates the processor is in
hibernate mode.
OD
I2C module 0 clock
OD
I2C module 0 data
OD
I2C module 1 clock
OD
I2C module 1 data
TTL
QEI module 0 index
TTL
QEI module 1 index
Power
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 µF or greater. When the
on-chip LDO is used to provide power to the
logic, the LDO pin must also be connected to
the VDD25 pins at the board level in addition
to the decoupling capacitor(s).
TTL
MII LED 0
524
November 30, 2007
Preliminary