LM3S6965_0711 Datasheet, PDF (10/578 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Figure 15-10. Master Burst RECEIVE .................................................................................................. 382
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 383
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 384
Figure 15-13. Slave Command Sequence ............................................................................................ 385
Figure 16-1. Ethernet Controller Block Diagram .................................................................................. 410
Figure 16-2. Ethernet Controller ......................................................................................................... 410
Figure 16-3. Ethernet Frame ............................................................................................................. 412
Figure 17-1. Analog Comparator Module Block Diagram ..................................................................... 453
Figure 17-2. Structure of Comparator Unit .......................................................................................... 454
Figure 17-3. Comparator Internal Reference Structure ........................................................................ 455
Figure 18-1. PWM Module Block Diagram .......................................................................................... 465
Figure 18-2. PWM Count-Down Mode ................................................................................................ 466
Figure 18-3. PWM Count-Up/Down Mode .......................................................................................... 467
Figure 18-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 467
Figure 18-5. PWM Dead-Band Generator ........................................................................................... 468
Figure 19-1. QEI Block Diagram ........................................................................................................ 502
Figure 19-2. Quadrature Encoder and Velocity Predivider Operation .................................................... 503
Figure 20-1. Pin Connection Diagram ................................................................................................ 518
Figure 23-1. Load Conditions ............................................................................................................ 538
Figure 23-2. I²C Timing ..................................................................................................................... 541
Figure 23-3. External XTLP Oscillator Characteristics ......................................................................... 543
Figure 23-4. Hibernation Module Timing ............................................................................................. 544
Figure 23-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 545
Figure 23-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 545
Figure 23-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 546
Figure 23-8. JTAG Test Clock Input Timing ......................................................................................... 547
Figure 23-9. JTAG Test Access Port (TAP) Timing .............................................................................. 547
Figure 23-10. JTAG TRST Timing ........................................................................................................ 547
Figure 23-11. External Reset Timing (RST) .......................................................................................... 548
Figure 23-12. Power-On Reset Timing ................................................................................................. 549
Figure 23-13. Brown-Out Reset Timing ................................................................................................ 549
Figure 23-14. Software Reset Timing ................................................................................................... 549
Figure 23-15. Watchdog Reset Timing ................................................................................................. 549
Figure 24-1. 100-Pin LQFP Package .................................................................................................. 550
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November 30, 2007
Preliminary