TH6503 Datasheet, PDF (5/24 Pages) List of Unclassifed Manufacturers – USB Low-Speed Interface

TH6503 USB Low-Speed Interface
Microcontroller
Interface
(continued)
1
SCK
0
Microcontroller
latches Data
on rising edge
of SCK
0
Bridge shifts
Data on falling
edge of SCK
1
1
SIN
0
1
SDO
0
1
SDI
0
Status0
Status1 Status2
Clear Interrupt Latch
SDI pulse with SIN=0:
- transfer StatusRegister to Serial Data Out
7
15
Bridge outputs
next Register (CntOutRegister)
Bit 0 on SDO
n+16
End of OUT Transfer
(OUT Tranfer after reading
the Status -and CntOutRegister
with SIN=0 clears
EP0 Out Done
Status7 CNT0
CNT7 FIFO Bit 0
Bit n
/INT
Figure 6. Complete Data OUT Transfer
1
SCK
0
1
SIN
0
1
SDO
0
1
SDI
0
Microcontroller
latches Data
on rising edge
of SCK
0
Bridge shifts
Data on falling
edge of SCK
CNT0
CNT1
Two SDI pulses with SIN=0:
- transfer CntOutRegister and OUT FIFO Bytes
to Serial Data Out
7
Bridge outputs
next Register (FIFO)
Bit 0 on SDO
End of OUT Transfer
(OUT Tranfer > 8 clocks
the Status -and CntOutRegister
with SIN=0 clears
EP0 Out Done
n+8
CNT7 FIFO Bit 0
Bit n
/INT
Figure 7. OUT Transfer, only CntOutRegister and OUT FIFO Bytes
Interrupt Function
If SIN = 1, the SDO pin can be used to generate an
interrupt signal. The interrupt is low active. It is
triggered if a control transfer is made from the USB
host or a control or interrupt transfer is made to the
USB host and one of the ID12, ID0 or OD bits has
been set in the StatusRegister <3-1> or at high
level of the WAKE pin. An interrupt signal is also
triggered on RESUME and USB_RESET.
The interrupt latch is reset on reading the status
register. If an interrupt is generated during read-
ing StatusRegister, this interrupt is latched and
the interrupt source is after new StatusRegister
reading visible.
A WAKE interrupt is only generated during the stop
state (bits SO and/or SMC in the BridgeConfig
Register are set).
5