TH6503 Datasheet, PDF (11/24 Pages) List of Unclassifed Manufacturers – USB Low-Speed Interface

TH6503 USB Low-Speed Interface
Register
Description
(continued)
CntOutRegister (read only)
second byte of each out transfer following an OUT packet sync
Bit
Bit
Number Mnemonic
7-6
OA
Reset
Status
0
5
TO
0
4
SET
0
3-0
OC3-0
0
Function
OUT Address
last valid OUT endpoint
? indicates the endpoint of actual OUT FIFO data
00 EP0
01 EP1
10 EP2
? only valid if EP1 OUT or EP2 OUT enabled, otherwise the internal
Revision number is visible
Toggle OUT
? is set if the data packet PID was DATA1 and reset if the data packet
PID was DATA0
? is latched with a valid EP0 SETUP or a OUT Token
Setup
? is set if a SETUP token is received
? is reset after OUT transfer to microcontroller
? no STALL or NAK is sent because it is not permitted on the SETUP
token
? the SO0 and SI0 (STALL EP0) flags in the USBFlagRegister are reset
on rising edge of Setup
? a SETUP token flash all IN FIFOs
EP0 OUT Byte Count
amount of OUT data received in the EP0 FIFO in bytes
? applicable values from 0 to 8
? a zero data transfer is identified 0
Internal Register
Adr/CntInRegister (write only)
first byte of each data in transfer following the IN packet sync
Bit
Number
7
Bit
Mnemonic
TI
6-4
RA2-0
3-0
IC3-0
Reset
Status
0
0
0
Function
Toggle IN
? is set if the data packet PID is DATA1 and reset if the data packet PID
is DATA0
Internal Address
destination address for a write operation to a TH6503 register or IN
FIIFO
IN Byte Count
number of data bytes to be transmitted without Adr/CntInRegister from
the microcontroller to the TH6503 if the destination address was an IN
FIFO
? applicable values from 0 to 8
? 0 indicates a zero data transfer to the USB host, but blocks the InFIFO
until ACK is received
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