TH6503 Datasheet, PDF (4/24 Pages) List of Unclassifed Manufacturers – USB Low-Speed Interface

TH6503 USB Low-Speed Interface
Microcontroller
Interface
(continued)
1
SCK
0
1
SIN
0
1
SDO
0
1
SDI
0
Bridge latches
Data on rising
edge of SCK
0
AC0
Microcontroller shifts
Data on falling
edge of SCK
1
AC1
AC2
Microcontroller outputs
Adr/CntInRegister Bit 0 / AC0
on SDI
7
/INT
AC7 Data Bit 0
n+8
End of IN Transfer
Bit n
Figure 4. Serial Data IN
Data OUT Transfer
(from the TH6503 to the microcontroller)
An impulse on the SDI link at SIN = 0 represents
the OUT packet sync for an OUT transfer. With the
falling SCK edge the data (LSB first) is shifted to
SDO and with rising SCK edge accepted by the
microcontroller. The StatusRegister is transferred
initially followed by the CntOutRegister and finally
the OUT FIFO data. If the transfer is terminated after
less than 8 clock pulses, only single StatusRegister
bits are read. Linear transfer is interrupted by SIN
= 1 and must be initiated with a new OUT packet
sync at SIN = 0. Two impulses on the SDI link
initiate a transfer of the CntOutRegisters and of the
following OUT FIFO bytes without the
StatusRegister. A zero data transfer is identified by
an OUT Count Byte value of 0. The end of a Data
OUT transfer clears the SET bit in the
CntOutRegister and the OD bit in the
StatusRegister to make the next USB OUT or
Setup transfer possible.
1
SCK
0
Microcontroller
latches Data
on rising edge
of SCK
0
Bridge shifts
Data on falling
edge of SCK
1
1
SIN
0
1
SDO
0
1
SDI
0
Status0
Status1 Status2
Clear Interrupt Latch
SDI pulse with SIN=0:
- copy StatusRegister to Shift Register for Serial Data Out
End of
Transfer
n
Status n
any break
after identify the
/INT source possible
/INT
n <= 7
Figure 5. OUT Transfer of StatusRegister
4