LM3S101 Datasheet, PDF (5/284 Pages) List of Unclassifed Manufacturers – Microcontroller

List of Figures
Figure 1-1. Stellaris High-Level Block Diagram ........................................................................................... 20
Figure 1-2. Stellaris System-Level Block Diagram....................................................................................... 25
Figure 2-1. CPU High-Level Block Diagram ............................................................................................... 27
Figure 2-2. TPIU Block Diagram .................................................................................................................. 28
Figure 5-1. JTAG Module Block Diagram .................................................................................................... 35
Figure 5-2. Test Access Port State Machine ............................................................................................... 38
Figure 5-3. IDCODE Register Format.......................................................................................................... 42
Figure 5-4. BYPASS Register Format ......................................................................................................... 42
Figure 5-5. Boundary Scan Register Format ............................................................................................... 43
Figure 6-1. External Circuitry to Extend Reset............................................................................................. 45
Figure 6-2. Main Clock Tree ........................................................................................................................ 48
Figure 7-1. Flash Block Diagram ................................................................................................................. 80
Figure 8-1. GPIO Module Block Diagram .................................................................................................... 94
Figure 8-2. GPIO Port Block Diagram.......................................................................................................... 95
Figure 8-3. GPIODATA Write Example........................................................................................................ 95
Figure 8-4. GPIODATA Read Example ....................................................................................................... 96
Figure 9-1. GPTM Block Diagram.............................................................................................................. 131
Figure 9-2. 16-Bit Input Edge Count Mode Example ................................................................................. 135
Figure 9-3. 16-Bit Input Edge Time Mode Example................................................................................... 136
Figure 9-4. 16-Bit PWM Mode Example .................................................................................................... 137
Figure 10-1. Watchdog Timer Block Diagram.............................................................................................. 160
Figure 11-1. UART Block Diagram .............................................................................................................. 183
Figure 11-2. UART Character Frame........................................................................................................... 184
Figure 12-1. SSI Block Diagram .................................................................................................................. 218
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer).......................................................... 220
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 221
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 222
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 222
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 223
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 223
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 224
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 224
Figure 12-10. National Semiconductor MICROWIRE Frame Format (Single Frame) ................................... 225
Figure 12-11. National Semiconductor MICROWIRE Frame Format (Continuous Transfers) ...................... 226
Figure 12-12. National Semiconductor MICROWIRE Frame Format, SSIFss Input Setup
and Hold Requirements........................................................................................................... 227
Figure 13-1. Analog Comparator Block Diagram ......................................................................................... 251
Figure 13-2. Structure of Comparator Unit................................................................................................... 252
Figure 13-3. Comparator Internal Reference Structure ............................................................................... 253
Figure 14-1. Pin Connection Diagram.......................................................................................................... 262
Figure 17-1. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 275
Figure 17-2. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 276
Figure 17-3. SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 276
Figure 17-4. JTAG Test Clock Input Timing................................................................................................. 277
Figure 17-5. JTAG Boundary Scan Timing .................................................................................................. 278
Figure 17-6. JTAG Test Access Port (TAP) Timing ..................................................................................... 278
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March 22, 2006
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