LM3S101 Datasheet, PDF (160/284 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S101 Data Sheet
10
10.1
Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The LM3S101 controller Watchdog Timer module consists of a 32-bit down counter, a
programmable load register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-
out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been
configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
Block Diagram
Figure 10-1. Watchdog Timer Block Diagram
Interrupt
System Clock
Control/ Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTLOAD
32-bit Down
Counter
0x00000000
Comparator
WDTVALUE
Prime Cell
WDTPCellID0
WDTPCellID1
WDTPCellID2
WDTPCellID3
Peripheral ID
WDTPeriphID0
WDTPeriphID1
WDTPeriphID2
WDTPeriphID3
WDT PeriphID4
WDTPeriphID5
WDTPeriphID6
WDTPeriphID7
March 22, 2006
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Preliminary