YMF740C Datasheet, PDF (40/44 Pages) List of Unclassifed Manufacturers – DS-1L

YMF740C
4-3. PCI Interface (Fig.3, 4)
Item
Symbol
Condition
Min. Typ. Max. Unit
PCICLK Cycle Time
PCICLK High Time
PCICLK Low Time
PCICLK Slew Rate
t_PCYC
t_PHIGH
t_PLOW
-
30
-
11
-
11
-
1
-
-
ns
-
ns
-
ns
4
V/ns
PCICLK to Signal Valid Delay
t_PVAL (Bused signal)
t_PVAL(PTP) (Point to Point)
2
-
11
ns
2
-
12
ns
Float to Active Delay
t_PON
2
-
-
ns
Active to Float Delay
t_POFF
-
-
28
ns
t_PSU (Bused signal)
7
-
-
ns
Input Setup Time to PCICLK
*10 (Point to Point) 10
-
t_{PSU(PTP) *11 (Point to Point)}
12
-
-
ns
-
ns
Input Hold Time for PCICLK
t_PH
0
-
-
ns
Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, C_L=50 pF
*10: This characteristic is applicable to REQ# and PCREQ# signal.
*11: This characteristic is applicable to GNT# and PCGNT# signal.
PCICLK
2.2 V
1.5 V
0.8 V
PCICLK
OUTPUT
Tri-State
OUTPUT
t _PHIGH
t _PLOW
t _PCYC
Fig.3: PCI Clock timing
1.5 V
t _PVAL
1.5 V
t _PON
t _POFF
INPUT
t _PSU
t _PH
1.5 V
Fig.4: PCI Bus Signals timing
January 14, 1999
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