PE97632 Datasheet, PDF (4/16 Pages) List of Unclassifed Manufacturers – 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

PE97632
Advance Information
Pin No.
46
47
48
Pin
Name
VDD
Fin
F_in
Valid
Mode
Both
Both
Type
(Note 1)
Input
Input
Description
Prescaler VDD.
Prescaler input from the VCO. 3.2 GHz max frequency.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50 Ω resistor directly to the ground plane.
49
GND
50
CEXT
51
LD
52
DOUT
Both
Both
Both
Downbond
Output
Output
Output
Ground
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
Data out function, enabled in enhancement mode.
53
VDD
(Note 1)
Output driver/VDD.
54
GND
55
PD_D
56
NC
57
PD_U
Both
Both
Both
Downbond
Output
Output
Ground
PD_D pulses down when fp leads fc. PD_U is driven to GND when CPSEL = “High”.
No Connect
PD_U pulses down when fc leads fp. PD_D is driven to GND when CPSEL = “High”.
58
GND
Downbond Ground
59
VDD
(Note 1)
Output driver/VDD.
60
VDD
(Note 1)
Phase detector VDD.
61
GND
62
fr
Both
Downbond
Input
Ground
Reference frequency input.
63
VDD
(Note 1)
Reference VDD.
64
VDD
(Note 1)
Digital core VDD.
GND
Downbond Ground
65
ENH
Both
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
66
NC
Both
No Connect
67
MS2_SEL ^Both
Input
MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
68
RND_SEL Both
Input
K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit
is the phase detector comparison frequency / 2¹⁹.
Note 1: All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 16
Document No. 70-0205-02 │ UltraCMOS™ RFIC Solutions