PE97632 Datasheet, PDF(10/16 Page) List of Unclassifed Manufacturers – 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

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PE97632 Datasheet, PDF (10/16 Pages) List of Unclassifed Manufacturers – 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

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While the E_WR input is âhighâ and the S_WR in-

put is âlowâ, serial input data (Sdata input), B0 to

B7, are clocked serially into the enhancement reg-

ister on the rising edge of Sclk, MSB (B0) first. The

enhancement register is double buffered to pre-

vent inadvertent control changes during serial

loading, with buffer capture of the serially entered

data performed on the falling edge of E_WR ac-

cording to the timing diagram shown in Figure 4.

After the falling edge of E_WR, the data provide

control bits as shown in Table 9 on page 10 will

have their bit functionality enabled by asserting

the Enh input âlowâ.

PE97632

Advance Information

Direct Interface Mode

Direct Interface Mode is selected by setting the

âDirectâ input âhighâ.

Counter control bits are set directly at the pins as

shown in Table 7 and Table 8.

Table 7. Secondary Register Programming

Interface

Mode

Enh

Pre_en M6 M5 M4 M3 M2 M1 M0 R3

A0 Addr

Direct

1 R5 R4 M8 M7 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0

Serial*

1 B0 B1 B2 B3

B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19

*Serial data clocked serially on Sclk rising edge while E_WR âlowâ and captured in secondary register on S_WR rising edge.

MSB (first in)

(last in) LSB

Table 8. Auxiliary Register Programming

Interface

Mode

Enh

K17

K16

K15

K14

K13

K12

K11

K10

Direct

1 K17 K16 K15 K14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1 K0

Serial*

B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17

*Serial data clocked serially on Sclk rising edge while E_WR âlowâ and captured in secondary register on S_WR rising edge.

Rsrv

B18

Rsrv

B19

Addr

MSB (first in)

(last in) LSB

Table 9. Enhancement Register Programming

Interface

Mode

Enh

Reserved

fp output

Power

Down

Counter

load

MSEL

output

fc output

Serial*

*Serial data clocked serially on Sclk rising edge while E_WR âhighâ and captured in the double buffer on E_WR falling edge.

LD Disable

MSB (first in)

(last in) LSB

Page 10 of 16

Document No. 70-0205-02 â UltraCMOSâ¢ RFIC Solutions

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