ICS9LPR502SGLFT Datasheet, PDF (4/29 Pages) List of Unclassifed Manufacturers – 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR INTEGRATED SERIES RESISTOR

ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
SSOP/TSSOP Pin Description (Continued)
PIN #
PIN NAME
29 CPU_STOP#/SRCC5
30 PCI_STOP#/SRCT5
31 VDDSRC
32 SRCC6
33 SRCT6
34 GNDSRC
35 SRCC7/CR#_E
36 SRCT7/CR#_F
37 VDDSRC_IO
38 CPUC2_ITP/SRCC8
39 CPUT2_ITP/SRCT8
40 NC
41 VDDCPU_IO
42 CPUC1_F
43 CPUT1_F
44 GNDCPU
45 CPUC0
46 CPUT0
47 VDDCPU
TYPE
I/O
I/O
PWR
OUT
OUT
PWR
I/O
I/O
PWR
OUT
OUT
N/A
PWR
OUT
OUT
PWR
OUT
OUT
PWR
DESCRIPTION
Stops all CPU Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap
on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as
follows:
0= CPU_STOP#
1 = SRC5
In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap
on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as
follows:
0= PCI_STOP#
1 = SRC5#
In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37.
VDD pin for SRC Pre-drivers, 3.3V nominal
Complement clock of low power differential SRC clock pair.
True clock of low power differential SRC clock pair.
Ground for SRC clocks
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of
SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must
first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled
(high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of
SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8
via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be
disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z),
the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus
configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
Power supply for SRC outputs. 1.05 to 3.3V +/-5%.
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The
function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup.
The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this
pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is
as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
No Connect
Supply for CPU outputs. 1.05 to 3.3V +/-5%.
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during
iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
IDT^TM/ICS^TM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
4
1125E—02/26/09