ICS9LPR502SGLFT Datasheet, PDF (24/29 Pages) List of Unclassifed Manufacturers – 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR INTEGRATED SERIES RESISTOR

ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
Byte 20 CK505 PLL3 Spread Spectrum Control Register
Bit Pin
Name
Description
Type
0
1
7
Reserved
6
SSP14
Reserved
RW
-
-
RW
-
-
5
SSP13
RW
-
-
4
SSP12
These Spread Spectrum bits will program the spread ^RW
-
-
3
SSP11
pecentage. Contact ICS for the correct values.
RW
-
-
2
SSP10
RW
-
-
1
SSP9
RW
-
-
0
SSP8
RW
-
-
Byte 21 M/N Enables
Bit Pin
Name
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
M/N Enable CPU
0
M/N Enable
Description
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
1
Enable
Enable
Byte 22 CPU M/N Programming
Bit Pin
Na me
Description
Type
0
1
7
N Div bit 8
PLL 1 M/N Programming
RW
-
-
6
N Div bit 9
(Intel PLL1 CPU)
RW
-
-
5
M Div Bit 5
4
M Div Bit 4
RW
-
-
RW
-
-
3
M Div Bit 3
RW
-
-
2
M Div Bit 2
RW
-
-
1
M Div Bit 1
RW
-
-
0
M Div Bit 0
RW
-
-
Byte 23 CPU M/N Programming
Bit Pin
Na me
Description
Type
0
1
7
N Div bit 7
PLL 1 M/N Programming
RW
-
-
6
N Div bit 6
(Intel PLL1 CPU)
RW
-
-
5
N Div bit 5
RW
-
-
4
N Div bit 4
RW
-
-
3
N Div bit 3
2
N Div bit 2
1
N Div bit 1
RW
-
-
RW
-
-
RW
-
-
0
N Div Bit 0
RW
-
-
Bytes 24-62 Reserved
Byte 63 Special Power Management Features (Rev P Silicon and Higher)
Bit Pin
Na me
Description
RW
0
1
7
Reserved
RW
6
Reserved
RW
5
Reserved
RW
4
Reserved
RW
3
Reserved
RW
2
Reserved
RW
1
SATA PLL
Power Management Feature
RW
off
on
0
XTAL PD Control
Controls XTAL on/off in legacy PD
RW
off
on
Note: Default is "off" for Rev P Silicon and higher.
*Accessing any SMBus bytes not shown in the datasheet could result in incorrect clock functions.
Default
0
X
X
X
X
X
X
X
Default
0
0
0
0
0
0
0
0
Default
X
X
X
X
X
X
X
X
Default
X
X
X
X
X
X
X
X
Default
0
0
0
0
0
0
Note
1
IDT^TM/ICS^TM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
24
1125E—02/26/09