ICS9LPR502SGLFT Datasheet, PDF (22/29 Pages) List of Unclassifed Manufacturers – 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR INTEGRATED SERIES RESISTOR

ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
Byte 10 CK505 Rev 0.85 functions (ICS Rev H silicon and higher)
Bit Pin
Name
Description
7
SRC5_EN Readback
Readback of SRC5 enable latch
6
Reserved
5
Reserved
4
Reserved
Reserved
3
Reserved
2
Reserved
1
CPU 1 Stop Enable
Enables control of CPU1 with CPU_STOP#
0
CPU 0 Stop Enable
Enables control of CPU 0 with CPU_STOP#
Type
R
RW
RW
RW
RW
RW
RW
RW
0
CPU/PCI Stop Enabled
TBD
TBD
TBD
TBD
TBD
Free Running
Free Running
1
SRC5 Enabled
TBD
TBD
TBD
TBD
TBD
Stoppable
Stoppable
Default
Latch
0
0
0
0
0
1
1
Byte 11 CK505 Rev 1.0 functions (ICS Rev P silicon and higher)
Bit Pin
Name
Description
7
Reserved
6
Reserved
5
Reserved
Reserved
4
Reserved
3
CPU2_iAMT_EN
Enables CPU2(ITP) output in iAMT state (M1)
2
CPU1_iAMT_EN
Enables CPU1 output in iAMT state (M1)
1
PCIe-Gen2
PCIe-Gen2 status
0
CPU2 Stop Enable Enables control of CPU2(ITP) with CPU_STOP#
Type
RW
RW
RW
RW
RW
RW
R
RW
0
TBD
TBD
TBD
TBD
Off in iAMT
Off in iAMT
non-Gen2
Free Running
1
TBD
TBD
TBD
TBD
Free running in iAMT
Free running in iAMT
PCIe Gen2 compliant
Stoppable
Default
0
0
0
0
0
1
0
1
Byte 12 Byte Count Register
Bit Pin
Name
Description
Type
0
7
Reserved
RW
6
Reserved
RW
5
BC5
RW
4
BC4
3
BC3
2
BC2
RW
Read Back byte count register,
RW
max bytes = 32
RW
1
BC1
RW
0
BC0
RW
1
Default
0
0
0
0
1
1
0
1
Byte 13 CK505 PLL1 M/N Programming Register
Bit Pin
Name
Description
Type
0
7
N Div8
N Divider 8
RW
-
6
N Div9
N Divider 9
RW
-
5
M Div5
RW
-
4
M Div4
The decimal representation of M and N Divider in Byte ^RW
-
3
M Div3
13 and 14 will configure the VCO frequency. Default ^RW
-
2
M Div2
at power up = latch-in or Byte 0 Rom table.
RW
-
1
M Div1
RW
-
0
M Div0
RW
-
1
Default
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
Byte 14 CK505 PLL1 M/N Programming Register
Bit Pin
Name
Description
Type
0
7
N Div7
RW
-
6
N Div6
RW
-
5
N Div5
The decimal representation of M and N Divider in Byte ^RW
-
4
N Div4
13 and 14 will configure the VCO frequency. Default ^RW
-
3
N Div3
at power up = latch-in or Byte 0 Rom table.
RW
-
2
N Div2
RW
-
1
N Div1
RW
-
0
N Div0
RW
-
1
Default
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
IDT^TM/ICS^TM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
22
1125E—02/26/09