AT84AD001CVEPW Datasheet, PDF (37/64 Pages) List of Unclassifed Manufacturers – Dual 8-bit 1 Gsps ADC

AT84AD001C
Table 10-3. 3-wire Serial Interface Data Setting Description (Continued)
Setting for Address: 000 D15 D14 D13 D12 D11 D10 D9⁽¹⁾ D8 D7 D6 D5 D4 D3 D2 D1 D0
Control wait bit
calibration⁽⁶⁾
X
X
a
b
X
X
0
XXXXXXXXX
In 1:2 DMUX
FDataReady
I & Q = Fs/4 ⁽⁹⁾
X
0
X
X
X
X
0
XXXXXXXXX
In 1:2 DMUX
FDataReady
I & Q = Fs/2 ⁽⁹⁾
X
1
X
X
X
X
0
XXXXXXXXX
Notes:
1. D9 must be set to “0”
2. Mode standby channel I: use analog input I Vini, Vinib and Clocki.
3. Mode standby channel Q: use analog input Q Vinq, Vinqb and Clockq.
4. Keep last calibration calculated value – no calibration phase: D11 = 0 and D10 = 1. No new calibration is required. The val-
ues taken into account for the gain and offset are either from the last calibration phase or are default values (reset values).
5. No calibration phase – no calibration value: D11 = 0 and D10 = 0. No new calibration phase is required. The gain and offset
compensation functions can be accessed externally by writing in the registers at address 010 for the offset compensation
and at address 011 for the gain compensation.
6. The control wait bit gives the possibility to change the internal setting for the auto-calibration phase:
For high clock rates (> 500 Msps) use a = b = 1.
For clock rates > 250 Msps and < 500 Msps use a = 1 and b = 0.
For clock rates > 125 Msps and < 250 Msps use a = 0 and b = 1.
For low clock rates < 125 Msps use a = 0 and b = 0.
7. If bit D2 “Chip version Test bit” is set to “0”, the output bit Cal should change to high level when the ADC corresponds to
AT84AD001C version (this function is not implemented in previous AT84AD001 and AT84AD001B versions).
8. When Channel I is in standby (D1 = 0, D0 = 1), the following modes are forbidden:
Clock I I & Q (D7 = 1, D6 = 0)
Clock I I & Clock IN Q (D7 = 0, D6 = X)
9. Default mode for AT84AD001C is now Fs/4 (previously Fs/2 for AT84AD001Bxxx series).
10.1.2
3-wire Serial Interface Timing Description
The 3-wire serial interface is a synchronous write-only serial interface made of three wires:
• sclk: serial clock input
• sldn: serial load enable input
• sdata: serial data input
The 3-wire serial interface gives write-only access to as many as 8 different internal registers of up to 16
bits each. The input format is always fixed with 3 bits of register address followed by 16 bits of data. The
data and address are entered with the Most Significant Bit (MSB) first.
The write procedure is fully synchronous with the rising clock edge of “sclk” and described in the write
chronogram (Figure 10-1 on page 38).
• “sldn” and “sdata” are sampled on each rising clock edge of “sclk” (clock cycle).
• “sldn” must be set to 1 when no write procedure is performed.
• A minimum of one rising clock edge (clock cycle) with “sldn” at 1 is required for a correct start of the
write procedure.
• A write starts on the first clock cycle with “sldn” at 0. “sldn” must stay at 0 during the complete write
procedure.
e2v semiconductors SAS 2010
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1006C–BDC–04/10