AT84AD001CVEPW Datasheet, PDF (34/64 Pages) List of Unclassifed Manufacturers – Dual 8-bit 1 Gsps ADC

AT84AD001C
Table 10-2.
Address
101
110
111
3-wire Serial Interface Address Setting Description (Continued)
Setting
Testability
Data3 to Data0 = 0000
Mode S/H transparent
Data7 = 0
Data8 = 0
Data5 to Data6 = XXX
Data15 to Data9 = XXX
OFF: Data4 = 0 ON: Data4 = 1
Built-In Test (BIT)
Data0 = 0
BIT Inactive
Data0 = 1 BIT Active
Data1 = 0
Static BIT
Data1 = 1 Dynamic BIT
If Data1 = 1, then Ports BI & BQ = Rising Ramp
Ports AI & AQ = Decreasing Ramp
If Data1 = 0, then Data2 to Data9 = Static Data for BIT
Ports BI & BQ = Data2 to Data9
Ports AI & AQ = NOT (Data2 to Data9)
Data15 to Data10 = XXX
Data Ready Delay Adjust (DRDA)
Data2 to Data0: clock I
Data5 to Data3: clock Q
Steps: 85 ps
000: –340 ps
100: 0 ps
111: +255 ps
Fine Sampling Delay Adjustment (FiSDA) on channel Q
Data10 to Data6: channel Q
Steps: 4 ps
Data4: sign bit
11000: –60 ps
Code 10000: 0 ps
Code 00000: 0 ps
Code 01111: +60 ps
Data15 to Data11 = XXX
Notes:
1. The Internal Settling Adjustment could change independently of the two analog sampling times (TA channels I and Q) of the
sample/hold (with a fixed digital sampling time) with steps of ±50 ps:
Nominal mode will be given by Data2…Data0 = 100 or Data5…Data3 = 100.
Data5…Data3 = 000 or Data2…Data0 = 000: sampling time is –200 ps compared to nominal.
Data2…Data0 = 111 or Data5…Data3 = 111: sampling time is 150 ps compared to nominal.
We recommend setting the ISA to 0 ps in 1:1 DMUX mode and to –100 ps in 1:2 DMUX mode to optimize the ADC’s
dynamic performance.
2. The Fine Sampling Delay Adjustment enables you to change the sampling time (steps of 4 ps) on channel Q more precisely,
particularly in the interleaved mode.
3. A Built-In Test (BIT) function is available to rapidly test the device’s I/O by either applying a defined static pattern to the dual
ADC or by generating a dynamic ramp at the output of the dual ADC. This function is controlled via the 3-wire bus interface
at the address 110. The maximum clock frequency in dynamic BIT mode is 1 Gsps.
Please refer to “Built-In Test (BIT)” on page 41 for more information about this function. Dynamic BIT works on channel I
when Clock I is applied and on channel Q when clock Q is applied.
4. The decimation mode enables you to lower the output bit rate (including the output clock rate) by a factor of 16, while the
internal clock frequency remains unchanged. The maximum clock frequency in decimation mode is 1 Gsps.
5. The “S/H transparent” mode (address 101, Data4) enables bypassing of the ADC’s track/hold. This function optimizes the
ADC’s performances at very low input frequencies (Fin < 50 MHz) with an increase of 2 dB in SNR.
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e2v semiconductors SAS 2010