AT84AD001CVEPW Datasheet, PDF (20/64 Pages) List of Unclassifed Manufacturers – Dual 8-bit 1 Gsps ADC

AT84AD001C
Figure 7-8. 1:2 DMUX Mode, Clock I ADC I, Clock IN ADC Q, Analog I ADC I, Analog Q
ADC Q
VINI
VINQ
TA
N+1
N
TA
M+1
M
CLKI
CLKIN
DOIA[0:7]
DOIB[0:7]
DOQA[0:7]
DOQB[0:7]
5.5 clock cycles (TPD) + TOD
N-4
N-2
4.5 clock cycles (TPD) + TOD
N
N+2
N-3
6 clock cycles (TPD) + TOD
M-4
5 clock cycles (TPD) + TOD
N-1
M-2
N+1
M
N+3
M+2
M-3
M-1
M+1
M+3
Programmable delay (DRDA)
CLKOI
(= CLKI/2)
Programmable delay (DRDA)
CLKOI
(= CLKI/4)
Notes:
1. Programmable delay is controlled via the 3WSI at address 111 (DRDA), refer to section 10 of the 0817G
datasheet.
2. CLKOQ is high impedance.
3. 3WSI Setting at address ‘000’:
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
0
0
1
0
1
1
1
1
0
0
20
1006C–BDC–04/10
e2v semiconductors SAS 2010