NT6862 Datasheet, PDF (34/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor

NT6862-5xxxx
15. I²C Bus Interface: DDC1 & DDC2B Slave Mode
Interface: ²IC bus interface is a two-wire, bi-directional
serial bus which provides a simple, efficient way for data
communication between devices, and minimizes the cost of
connecting among various peripheral devices. NT6862
provides two I²C channels. Both of them are shared with
I/O pins and their structures are open drain. When the
system is reset, these channels are originally general I/O
pins structure. All of these I²C bus function will be activated
only after their ENDDC bits are cleared to '0' (CH0/1CON
registers).
DDC1 & DDC2B+ function: Two modes of operation have
been implemented in NT6862, uni-directional mode (DDC1
mode) and bi-directional mode (DDC2B+ mode). These
channels will be activated as DDC1 function initially when
users enable DDC function. These channels will switch
automatically to DDC2B+ function from DDC1 function
when a low pulse greater than 500ns is detected on the
SCL line. Users can start a master communication directly
from DDC1 communication by clearing MODE bit in the
CH0/1CLK control register.
The channels can return to DDC1 function when users set
the MD1/ 2 bit to '1' in the CH0/1CON registers.
15.1. DDC1 bus interface
Vsync input and SDA pin: In DDC1 function, the Vsync pin
is used as input clock pin and SDA pin is used as data
output pin. This function comprises two data buffers: one is
preloading data buffer for putting one byte data in advance
by user (CH0/1TXDAT), and the other is shift register for
shifting out one bit data to SDA line, which users can not
access directly. These two data buffer cooperate properly.
For the timing diagram please refer to Figure 15.1. After
system resets, the I²C bus interface is in DDC1 mode.
Data transfer: At first, user must put one byte transmitted
data into CH0/1TXDAT register in advance, and activate
I²C bus by setting ENDDC bit to '0'. Then open INTTX0/1
interrupt source by setting INTTX0/1 to '1' in the IEIRQ0/1
registers. On the first 9 rising edges of Vsync, system will
shift out invalid bit in shift register to SDA pin to empty shift
register. When shift register is empty and on next rising
edge of Vsync, it will load data in the CH0/1TXDAT
registers to internal shift register. At the same time, NT6862
will shift out MSB bit and generate an INTTX0/1 interrupts
to remind user to put next byte data into CH0/1TXDAT
register. After eight rising clocks, there have been eight bits
shifted out in proper order and shift register becomes
empty again. At the ninth rising clock, it will shift the ninth
bit (null bit '1') out to SDA. And on the next rising edge of
Vsync clock, system will generate an INTTX0/1 interrupts
again. By the same way, NT6862 will load new data from
CH0/1TXDAT registers to internal shift register and shift out
one bit right away. Beware that user should put one new
data into CH0/1TXDAT registers properly before the shift
register is empty (the next INTTX0/1 interrupt). If not, the
hardware will tansmit the last byte data repeatedly.
Vsync clock: Only in the separate SYNC mode, can the
Vsync pulse be used as data transfer clock, its frequency
can be up to 25KHz maximum. In composite Vsync mode,
NT6862 can not transmit any data to SDA pin, regardless
whether the Vsync can be extracted from composite Hsync
signal.
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