NT6862 Datasheet, PDF (30/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor

NT6862-5xxxx
Self testing pattern: At activating free running function, the system will generate the testing pattern when clearing the
ENPAT bit. The PORT14 pin will switch from I/O pin to pattern output pin (push-pull structure). The system provides four
types of testing patterns. Refer the figure below. Set the PAT0 bits to select the pattern type (Figure 13.8). If the free run
function has not been enabled, any change of ENPAT & PAT0 bits will be invalid. Refer the Figure 13.9 for the porch time
of video pattern.
PAT0
Test Pattern
Note
0
(1)
Only activated on ENPAT bit be cleared
1
(2)
The porch of self test pattern are listed below:
Free Running
Freq.
1
Front Porch of
VBLANK
128µs
BACK Porch of
VBLANK
864µs
2
90.5 µs
589µs
3
51µs
528µs
4
51.5 µs
596µs
5
46.6 µs
515µs
Front Porch of
HBLANK
460ns
1.18µs
424ns
185ns
436ns
BACK Porch of
HBLANK
2.00µs
1.93µs
1.92µs
1.94µs
1.94µs
VSYNC
PULSE WIDTH
64µs
64µs
64µs
64µs
64µs
HSYNC
PULSE WIDTH
1µs
1µs
1µs
1µs
1µs
Mode change detection: The system provides a hardware detection of Sync signal changed and support user to respond to
this transition an proper process as soon as possible. There are three kinds of detections to set INTMUTE bit.
Hsync counter: Users can enable HDIFF comparison by clearing ENHDIFF bit and then preload an difference value to
HDIFF0-3 bits in the AUTOMUTE control register ($000E). The system will latch the new value of Hsync counter and
compare it with the last latched value. If this difference is great than this user defined value at HDIFF0-3 bits, system will set
the INTMUTE interrupt bit.
H/V polarity: Users can enable polarity detection by clearing ENPOL bit. The system will set the INTMUTE bit when the
polarity of Hsync or Vsync have been changed.
H/V counter overflow: Users can enable the detection of sync counters overflow by clearing ENOVER bit. The system will
set the INTMUTE bit whenever the counter of Hsync or Vsync has been overflowed.
The above three sources of setting this INTMUTE bit can be enabled or disabled by user. If user opens this interrupt, the
system will generate an NMI interrupt to remind users anytime. At user's manipulation, a software debounce to confirm the
transition of sync signal for one more times will make this system stable and reliable, but it will affect the response time. After
system reset, this 'automute' function will be disabled and the HDIFF0-2 control bits will be cleared to ' $0F'.
HALFHI
HALFHO: Half freq. Output signal (50% duty)
HALFHO output signal when NOHALF bit clear to LOW
(the same signal as in the HALFHI pin)
Figure 13.7. Half Freq. Sync. Waveform
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