NT6862 Datasheet, PDF (14/57 Pages) List of Unclassifed Manufacturers – 8-Bit Microcontroller for Monitor

NT6862-5xxxx
8. A/D Converters
The structure of these analog to digital converters is 6-bit
successive approximation. Analog voltage is supplied from
external sources to the A/D input pins and the result of the
conversion is stored in the 6-bit data latch registers ($0011
& $0014). The A/D channels are activated by clearing the
correspondent control bits in the ENADC control register.
When users write '0' to one of the enable control bits, its
correspondent I/O pin or DAC will be switched to the A/D
converter input pin (ADC0 & ADC1 shared with PORT10 &
PORT 11; ADC2 & ADC3 shared wit DAC0 & DAC1).
Conversion will be started by clearing CSTA bit
(CONVERSION START) in the ENADC control register.
When conversion is finished, system will set this INTADC
bit. Users can monitor this bit to get the valid A/D
conversion data in the AD latch registers ($0011 - $0014).
Users can also open interrupt sources to remind users to
get the stable digital data. Note that latched data is only
available at the activated A/D channel.
The analog voltage to be measured should be stabled
during the conversion operation and the variation will not
exceed LSB for the best accuracy in measurement.
Addr. Register INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0010
ENADC
FFH _CSTA
-
-
-
ENADC3 ENADC2
ENADC1 ENADC0
W
$0011 AD0 REG C0H
-
-
AD05 AD04
AD03
AD02
AD01
AD00
R
$0012 AD1 REG 00H
-
-
AD15 AD14
AD13
AD12
AD11
AD10
R
$0013 AD2 REG 00H
-
-
AD25 AD24
AD23
AD22
AD21
AD20
R
$0014 AD3 REG 00H
-
-
AD35 AD34
AD33
AD32
AD31
AD30
R
$001B
IEIRQ2
00H
-
-
-
-
INTADC
INTV
INTE1
INTMR R/W
$001E
IRQ2
00H
-
-
-
-
INTADC
INTV
INTE1
INTMR
R
-
-
-
-
CLRADC CLRV
CLRE1
CLRMR
W
Reference ADC Table (V_DD = 5.0V)
15
1.53V
1C
2.07V
23
2.62V
2A
3.16V
16
1.62V
1D
2.16V
24
2.70V
2B
3.25V
17
1.69V
1E
2.23V
25
2.77V
2C
3.33V
18
1.76V
1F
2.31V
26
2.85V
2D
3.40V
19
1.84V
20
2.39V
27
2.93V
2E
3.48V
1A
1.92V
21
2.47V
28
3.01V
2F
3.56V
1B
2.00V
22
2.54V
29
3.09V
30
3.64V
Note: It is strongly recommended that the ADC’s input signal should be allocated in the ADC’s linear voltage range
(1.5V - 3.5V) to obtain a stable digital value. Do not use the outer ranges (0V - 1.4V & 3.6V - 5.0V) in which the
converted digital value is not guaranteed.
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