STK22C48 Datasheet, PDF (3/11 Pages) List of Unclassifed Manufacturers – 2K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM

SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
1
t_ELQV
2
t_AVAVg
3
t_AVQVh
4
t_GLQV
5
t_AXQXh
6
t_ELQX
7
t_EHQZi
8
t_GLQX
9
t_GHQZi
10
t_ELICCHf
11
t_EHICCLf
t_ACS
t_RC
t_AA
t_OE
t_OH
t_LZ
t_HZ
t_OLZ
t_OHZ
t_PA
t_PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled^{g, h}
ADDRESS
DQ (DATA OUT)
5
t_AXQX
2
t_AVAV
3
t_AVQV
SRAM READ CYCLE #2: E Controlled^g
ADDRESS
E
6
t_ELQX
2
t_AVAV
1
t_ELQV
G
DQ (DATA OUT)
I_CC
4
8
t_GLQV
t_GLQX
10
t_ELICCH
STANDBY
ACTIVE
STK22C48
STK22C48-25
MIN MAX
25
25
25
10
5
5
10
0
10
0
25
(V_CC = 5.0V ± 10%)^e
STK22C48-35
MIN MAX
STK22C48-45
UNITS
MIN MAX
35
45
ns
35
45
ns
35
45
ns
15
20
ns
5
5
ns
5
5
ns
13
15
ns
0
0
ns
13
15
ns
0
0
ns
35
45
ns
DATA VALID
11
t_EHICCL
7
t_EHQZ
9
t_GHQZ
DATA VALID
December 2002
3 Document Control # ML0004 rev 0.0