S93662 Datasheet, PDF (3/14 Pages) List of Unclassifed Manufacturers – Voltage Monitor and Reset Controller

S93662/S93663
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the S93662/663
will come out of the high impedance state and, will first
output an initial dummy zero bit, then begin shifting out
the data addressed (MSB first). The output data bits
will toggle on the rising edge of the SK clock and
are stable after the specified time delay
(tPD0 or tPD1).
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of 250ns (tCSMIN). The falling edge of CS will
start automatic erase and write cycle to the memory
location specified in the instruction. The ready/busy
status of the S93662/663 can be determined by select-
ing the device and polling the DO pin.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deselected for a minimum
of 250ns (t_CSMIN). The falling edge of CS will start the
auto erase cycle of the selected memory location. The
ready/busy status of the S93662/663 can be deter-
mined by selecting the device and polling the DO pin.
Once cleared, the content of a cleared location returns
to a logical “1” state.
Erase/Write Enable and Disable
The S93662/663 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all S93662/663 write
and clear instructions, and will prevent any accidental
tSKHI
t _SKLOW
t _CSH
SK
t _DIS
DI
VALID
tCSS
CS
VALID
tDIH
t _DIS
tPD0,t _PD1
tCSMIN
DO
DATA V ALID
Figure 1. Sychronous Data Timing
2012 ILL 3 1.0
SK
CS
AN AN_–1
A0
DI
11
0
tCS
STANDBY
HIGH-Z
tPD0
DO
0
tHZ
HIGH-Z
DN DN_–1
D1 D0
Figure 2. Read Instruction Timing
2012 ILL4 1.0
2012 2.0 4/18/00
3