COIC5130A Datasheet, PDF (3/20 Pages) List of Unclassifed Manufacturers – Programmable Reed-Solomon Error Correction Encoder and Decoder

COic5130A Specifications
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The number of data symbols ( k ) of succeeding blocks can be changed
as desired at any time. This will change the code rate for the blocks, but
to change the correction power ( r ) the section must be re-initialized.
This can also be done at any time, but any blocks in process at that time
will be lost.
Encoder Duplex Operation
Half Duplex operation can be achieved on a single bi-directional chan-
nel at a maximum transmission rate equal toone half of the symbol
clock. Allowing for transmission and circuit switching delays, data can
be switched from the unit encoder to the decoder on any symbol
boundary. External data switching and control circuits will be required
to control data flow and device enables.
Full duplex at full clock rate can be implemented but requires two data
carriers or echo cancellation.
Encoder Pass Through Mode
Any number of symbols can be passed through the encoder without any
encoding if the Enable In (EnlnA) is held high and enable out ( EnOutA)
is held low while the symbols are clocked into the section. This will
allow the maximum data transfer rate, but will not provide any error
correction (t=0 ). To end pass through mode operation EnlnA must be
brought high, which will start the encoding process. This must be at the
beginning of a block for correct operations. Pass through mode may be
invoked at any time but any blocks in process when this mode is start-
ed will not be encoded properly and will not be able to be decoded.
Decoder Functional Description
COic5130A includes a high data rate programmable Forward Error
Correction devices that can decode Reed-Solomon code blocks of up to
255 eight bit data symbols. It provides corrections of up to 10 symbol
errors per block at data rates up to 320 Mbs. Blocks with more errors
than are correctable are so flagged with data outputted as received ( no
corrections ). Note: blocks must contain at least 8 parity symbols, except
when operating in bypass mode.
The decoder input code block will contain the transmitted data and par-
ity symbols, including corruption by channel noise ( errors ). A symbol
error is corrected the same regardless of the number of incorrect bits in
the symbol and decoding time is the same regardless of the number of
errors in a block. Decoder output data will be corrected data plus cor-
rected parity or block error data. Error location and correction data is
also provided. No clock other than the data clock is required. Input and
output are one byte per clock cycle.
COic5130A uses the primitive polynomial Px = x 8 + x4 + x 3 + x2 +
x0 which complies with SMPTE D-1 / D-2 Digital Video Standards,
DVB,DBS, DAVIC, DSL, ANSI ID-1 / ID-2, and MIL STD 2179A. The
COic5130A is functionally compatible with the COic5127 encoder and
COic5128 decoder as well as the T=5 AMPEX 1295126-01. It includes
features not found in that device, and using r = 20 corrects up to 10
errors per block.
r-1
Devices use the generator polynomial : G ( x) = Õ ( x - µ i )
i=0
Decoder Functional Block Diagram
DIN7 - DIN0
CLK
FIFO
Error Locator
& Evaluator
Error
Correct
DOUT7- DOUT0
MAG7- MAG0
LOC
DATAEN
Control
RESET SHORT1
DATARDY
CORR
P0 - P4
ENABIN STATEN SHORT2
Decoder Features
• Supports 8 bit symbol Reed Solomon codes ( N, N-r ) with 0 < r < 20
and N < 255, N= symbols per block including parity, r = number of
parity symbols (Note: r is often called 2t)
• Corrects up to 10 errors per block
• COic5128A has 3 selectable latencies:
Default ( Ampex / AHA ) = 2N + 5r + 33 clock cycles with a
minimum block length of 5r + 15
Latency 1 = 2N + 2r + 13 clock cycles with a minimum block
length of 2r + 13
Latency 2 = 3N /2 +3r/2 + 15 clock cycles with a minimum
block length of 3r/2 + 15
• Contains complete decoder device. No external memory or control
required after initialization
• Data rates up to 40 MBS ( 320 Mbs ) with 0 to 40 Mhz symbol clock
• End of Block flag eases applications
• Input and output data are at the identical rate and operates on data
clock only
• Provides Pass Through Mode ( no correction ) switching on-the-fly
• Latency is constant regardless of error patterns
• Allows code rate change ( less data, same parity ) on-the-fly