STAC9721 Datasheet, PDF (26/48 Pages) List of Unclassifed Manufacturers – Stereo AC 97 Codec With Multi-Codec Option

SigmaTel, Inc.
Data Sheet
STAC9721
4.4.8.1 External Amplifier Power Down Control
The EAPD bit D15 of the Powerdown Control/Status Register (Index 26h) directly
controls the output of the EAPD output, pin 45, and produces a logical “1” when this bit
is set to logic high. This function is used to control an external audio amplifier power
down. EAPD = 0 places approximately 0V on the output pin, enabling an external audio
amplifier. EAPD = 1 places approximately DVDD on the output pin, disabling the
external audio amplifier. Audio amplifiers that operate with reverse polarity will likely
require an external inverter to maintain software driver compatibility.Extended Audio ID
Register (Index 28)
4.4.9
Extended Audio Register (Index 28h)
The Extended Audio ID register is a read only register. ID1 and ID0 echo the
configuration of the codec as defined by the programming of pins 45 and 46 externally.
“00” returned defines the codec as the primary codec, while any other code identifies the
codec as one of three secondary codec possibilities. The AMAP bit, D9, will return a 1
indicating that the codec supports the optional “AC’97 2.1 compliant AC-link slot to
audio DAC mappings”. The default condition assumes that 0, 0 are loaded in the MC1
and MC0 bits of the Multi-Channel Programming Register (Index 74h). With 0s in the
MCx bits, the codec slot assignments are as per the AC’97 specification
recommendations. If the MCx bits do not contain 0s, the slot assignments are as per the
table in the section describing the Multi-Channel Programming Register (Index 74h).
Table 17. Extended Audio ID Register Functions
BIT
FUNCTION
IDx
AMAP
External CID pin status
Multi-channel slot support
4.4.10 Revision (Index 6Ch)
The device Revision register (index 6Ch) contains a software readable revision-specific
code used to identify performance, architectural, or software differences between various
device revisions. Bits 7:0 of the Revision register are user readable; bits 15:8 are not
used at this time and will return zeros when read. The lower order bits of the Revision
Register (bits 7:0) are currently set to 00h, and will likely change if there are any
STAC9721/23 metal revisions.
4.4.11 Analog Special Register (Index 6Eh)
The Analog Special Register has two read/write bits used to control two functions
specific to the STAC9721/23. DAC –6dB is used to program the DAC outputs to a –6dB
signal level relative to the value of gain already programmed. Similarly, ADC –6dB
attenuates any signal input to the ADC by 6dB.
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