STAC9721 Datasheet, PDF (12/48 Pages) List of Unclassifed Manufacturers – Stereo AC 97 Codec With Multi-Codec Option

SigmaTel, Inc.
Data Sheet
STAC9721
SYNC
OUTGOING STREAMS
INCOMING STREAMS
TAG PHASE
TAG
CMD
ADR
CMD
DATA
PCM
LEFT
TAG
STATUS
ADR
STATUS
DATA
PCM
LEFT
PCM
RT
PCM
RT
NA
PCM
CTR
PCM
LSURR
PCM
RSURR
PCM
LFE
PCM
LALT
PCM
RALT
RSVD
NA
NA
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
DATA PHASE
Figure 4. AC'97 Standard Bi-directional Audio Frame
3.1.1 AC-Link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the multiplexed bundles of all digital
output data targeting the STAC9721/23 DAC inputs, and control registers. Each audio
output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special
reserved time slot containing 16 bits that are used for AC-Link protocol infrastructure.
Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the
validity for the entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the
current audio frame contains at least one slot time of valid data. The next 12 bit positions
sampled by the STAC9721/23 indicate which of the corresponding 12 times slots contain
valid data. In this way data streams of differing sample rates can be transmitted across
AC-Link at its fixed 48kHz audio frame rate. The following diagram illustrates the time
slot based AC-Link protocol.
Figure 5. AC-Link Audio Output Frame
Tag Phase
Data Phase
20.8 uS (48 kHZ)
SYNC
BIT_CLK
12.288 MHz
SDATA_OUT
valid
Frame
slot1
slot2
slot(12) "0" CID1 CID0 19
"0"
End of previous audio frame
Time Slot "Valid" Bits
("1" = time slot contains valid PCM data)
Slot 1
19
"0" 19
"0"
Slot 2
Slot 3
19
"0"
Slot 12
e
A new audio output frame begins with a low to high transition of SYNC. SYNC is
synchronous to the rising edge of BIT_CLK. On the immediately following falling edge
of BIT_CLK, the STAC9721/23 samples the assertion of SYNC. This following edge
marks the time when both sides of AC-Link are aware of the start of a new audio frame.
On the next rising edge of BIT_CLK, the AC'97 controller transitions SDATA_OUT into
the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to
AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the STAC9721/23
on the following falling edge of BIT_CLK. This sequence ensures that data transitions,
and subsequent sample points for both incoming and outgoing data streams are time
aligned.
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04/07/00
04/07/00