ISD5008 Datasheet, PDF (26/47 Pages) List of Unclassifed Manufacturers – SINGLE CHIP VOICE RECORD PLAYBACK DEVICE 4-, 5-, 6-, AND 8- MINUTE DURATIONS

ISD5008 Product
D9 and D10 of CFG1. They control the
SUM1 MUX. (f). Bits VOL0, VOL1 and VOL2
are bits D11, D12 and D13 of CFG1. They
control the setting of the Volume Control.
(g). Bits VLS0 and VLS1 are bits D14 and D15
of CFG1. They control the Volume Control
MUX.
The end result of the above set up is
CFG0=0100 0100 0000 1011 (hex 440B)
and
CFG1=0000 0001 1110 0011 (hex 01E3).
Since both registers are being loaded, CFG0 is
loaded followed by the loading of CFG1. These
two registers must be loaded in this order. The in-
ternal set up for both registers will take effect syn-
chronously with the rising edge of SS.
5.2 CALL RECORD
The call record mode adds the ability to record
the incoming phone call. In most applications,
the ISD5008 would first be set up for Feed Through
Mode as described above. When the user wishes
to record the incoming call, the set up of the chip
is modified to add that ability. For the purpose of
this explanation, we will use the 6.4 kHz sample
rate during recording.
The block diagram of the ISD5008 shows that the
Multilevel Storage array is always driven from the
SUM2 SUMMING amplifier. The path traces back
from there through the LOW PASS Filter, THE FILTER
MUX, THE SUM1 SUMMING amplifier, the SUM1
MUX, then from the ANA in amplifier. Feed Through
Mode has already powered up the ANA IN amp
so we only need to power up and enable the path
to the Multilevel Storage array from that point:
1. Select the ANA IN path through the SUM1
MUX—Bits S1S0 and S1S1 control the state
of the SUM1 MUX. These are bits D9 and
D10 respectively of CFG1 and they should
be set to the state where both D9 and D10
are ZERO to select the ANA IN path.
2. Select the SUM1 MUX input (only) to the S1
SUMMING amplifier—Bits S1M0 and S1M1
control the state of the SUM1 SUMMING
amplifier. These are bits D7 and D8 respec-
tively of CFG1 and they should be set to the
state where D7 is ONE and D8 is ZERO to se-
lect the SUM1 MUX (only) path.
3. Select the SUM1 SUMMING amplifier path
through the FILTER MUX—Bit FLS0 controls
the state of the FILTER MUX. This is bit D4 of
CFG1 and it must be set to ZERO to select
the SUM1 SUMMING amplifier path.
4. Power up the LOWPASS FILTER—Bit FLPD
controls the power up state of the LOWPASS
FILTER stage. This is bit D1 of CFG1 and it
must be set to ZERO to power up the LOW
PASS FILTER STAGE.
5. Select the 6.4 kHz sample rate—Bits
FLD0 and FLD1 select the Low Pass filter set-
ting and sample rate to be used during
record and playback. These are bits D2
and D3 of CFG1. To enable the 6.4 kHz
sample rate, D2 must be set to ONE and
D3 set to ZERO.
6. Select the LOW PASS FILTER input (only)
to the S2 SUMMING amplifier—Bits S2M0
and S2M1 control the state of the SUM2
SUMMING amplifier. These are bits D5 and
D6 respectively of CFG1 and they should
be set to the state where D5 is ZERO and D6
is ONE to select the LOW PASS FILTER (only)
path.
In this mode, the elements of the original PASS
THROUGH mode do not change. The sections of
the chip not required to add the record path re-
main powered down. In fact, CFG0 does not
change and remains
CFG0=0100 0100 0000 1011 (hex 440B).
CFG1 changes to
CFG1=0000 0000 1100 0101 (hex 00C5).
Since CFG0 is not changed, it is only necessary to
load CFG1. Note that if only CFG0 was changed,
it would be necessary to load both registers.
ISD
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