LM3S102 Datasheet, PDF (243/335 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S102 Data Sheet
Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
SSI Control 1 (SSCR1)
Offset 0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SOD MS SSE LBM
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
SOD
2
MS
Type
RO
R/W
R/W
Reset
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In
multiple-slave systems, it is possible for the SSI master to
broadcast a message to all slaves in the system while
ensuring that only one slave drives data onto the serial output
line. In such systems, the TXD lines from multiple slaves
could be tied together. To operate in such a system, the SOD
bit can be configured so that the SSI slave does not drive the
SSITx pin.
0: SSI can drive SSITx output in Slave Output mode.
1: SSI must not drive the SSITx output in Slave mode.
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified
only when SSI is disabled (SSE=0).
0: Device configured as a master.
1: Device configured as a slave.
October 6, 2006
243
Preliminary