YMF744B Datasheet, PDF (23/60 Pages) List of Unclassifed Manufacturers – DS-1S

YMF744B
4A-4Bh: DS-1S Power Control 1
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 - JSR -
-
- DPLL - DMC
b0................DMC: Disable Master Clock Oscillation
Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz).
“0”: Normal
(default)
“1”: Disable
b2................DPLL: Disable PLL Clock Oscillation
Setting this bit to “1” disables the oscillation of PLL.
“0”: Normal
(default)
“1”: Disable
b6................JSR: Joystick Reset
This bit controls reset of the flip-flop circuit following the analog comparator stage on the joystick port.
The Initial value is set to “0” immediately after power on reset or hardware reset.
“0”: Normal
(default)
“1”: Resets the flip-flop circuit following the analog comparator stage on the joystick port
b8................PR0: AC’97 Power Down Control 0
This bit controls the power state of the ADC and Input Mux in the Primary AC’97.
“0”: Normal
(default)
“1”: Power down
b9................PR1: AC’97 Power Down Control 1
This bit controls the power state of the DAC in the Primary AC’97.
“0”: Normal
(default)
“1”: Power down
b10..............PR2: AC’97 Power Down Control 2
This bit controls the power state of the Analog Mixer (Vref still on) in the Primary AC’97. This power
state retains the Reference Voltage of the AC’97.
“0”: Normal
(default)
“1”: Power down
b11..............PR3: AC’97 Power Down Control 3
This bit controls the power state of the Analog Mixer (Vref off) in the Primary AC’97. This power
state removes Reference Voltage of the AC’97.
“0”: Normal
(default)
“1”: Power down
February 3, 1999
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