CH7009A Datasheet, PDF (23/46 Pages) List of Unclassifed Manufacturers – Chrontel CH7009 DVI / TV Output Device

CHRONTEL
CH7009A
Table 9: IIC Register Map w/o Macrovision
Register
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
31h
32h
33h
35h
36h
37h
48h
49h
4Ah
4Bh
Bit 7
IR2
VBID
SAV7
HP7
VP7
BL7
MEM2
M7
N7
FSCI31
FSCI23
FSCI15
FSCI7
CIV23
CIV15
CIV7
Bit 6
IR1
VOF0
CFRB
SAV6
HP6
VP6
BL6
MEM1
M6
N6
FSCI30
FSCI22
FSCI14
FSCI6
CIV22
CIV14
CIV6
Bit 5
IR0
CFF1
CVBWB
SAV8
SAV5
HP5
VP5
BL5
MEM0
M5
N5
FSCI29
FSCI21
FSCI13
FSCI5
CIV25
CIV21
CIV13
CIV5
GOENB1
IBS
HPIE2
XOSC1
SHF2
TPPD3
TPVCO7
DVID2
GOENB0
DES
XOSC2
XOSC0
SHF1
TPPD2
TPVCO6
DVID1
TPLPF3 TPLPF2
TPVCO10 TPVCO9
GPIOL1
SYO
DVIT
SHF0
TPPD1
TPVCO5
DVID0
TPVT5
TPLPF1
TPVCO8
DVIP
VID7
DID7
DVIL
VID6
DID6
TV
VID5
DID5
Bit 4
VOS1
CFF0
CBW
HP8
SAV4
HP4
VP4
BL4
N9
M4
N4
FSCI28
FSCI20
FSCI12
FSCI4
CIV24
CIV20
CIV12
CIV4
GPIOL0
VSP
DACT3
SYNCO1
BCOEN
TPPD0
TPVCO4
DVII
TPVT4
TPLPF0
ResetIB
DACPD3
VID4
DID4
Bit 3
VOS0
YFFT1
YSV1
VP8
SAV3
HP3
VP3
BL3
N8
M3
N3
FSCI27
FSCI19
FSCI11
FSCI3
CIVC1
CIV19
CIV11
CIV3
M/S*
XCMD3
HPIR
HSP
DACT2
SYNCO0
BCOP
CTL3
TPVCO3
TPVT3
ResetDB
DACPD2
VID3
DID3
Bit 2
SR2
YFFT0
YSV0
TE2
SAV2
HP2
VP2
BL2
CE2
M8
M2
N2
FSCI26
FSCI18
FSCI10
FSCI2
CIVC0
CIV18
CIV10
CIV2
MCP
XCMD2
HPIE
IDF2
DACT1
DACG1
BCO2
CTL2
TPVCO2
TPVT2
RSA
DACPD1
VID2
DID2
Bit 1
SR1
YFFNT1
YCV1
TE1
SAV1
HP1
VP1
BL1
CE1
PLLCPI
M1
N1
FSCI25
FSCI17
FSCI9
FSCI1
PALN
CIV17
CIV9
CIV1
PCM
XCMD1
POUTE
IDF1
DACT0
DACG0
BCO1
CTL1
TPVCO1
TPCP1
TPVT1
TSTP1
DACPD0
VID1
DID1
Bit 0
SR0
YFFNT0
YCV0
TE0
SAV0
HP0
VP0
BL0
CE0
PLLCAP
M0
N0
FSCI24
FSCI16
FSCI8
FSCI0
CIVEN
CIV16
CIV8
CIV0
XCM
XCMD0
POUTP
IDF0
SENSE
DACBP
BCO0
CTL0
TPVCO0
TPCP0
TPVT0
TSTP0
FPD
VID0
DID0
All register bits not defined in the register map are reserved bits, and should be left at the default value.
201-0000-035 Rev 1.1, 5/8/2000
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