CH7009A Datasheet, PDF (20/46 Pages) List of Unclassifed Manufacturers – Chrontel CH7009 DVI / TV Output Device

CHRONTEL
Transfer Protocols (continued)
AR[6:0]
Specifies the Address of the Register to be Accessed.
CH7009A
This register address is loaded into the Address Register of the CH7009. The R/W access, which
follows, is directed to the register specified by the content stored in the Address Register.
The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and
AutoInc and alternating operation.
CH7009 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the master-
transmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slave-
receiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the
HIGH period of the clock pulse. The CH7009 always acknowledges for writes (see Figure 10). Note that the
resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
SD Data Output
By Master-Transmitter
SD Data Output
By the CH7009
SC from
1
Master
Start
Condition
not acknowledge
acknowledge
2
8
9
clock pulse for
acknowledgment
Figure 10: Acknowledge on the Bus
Figure 11 shows two consecutive alternating write cycles. The byte of information, following the Register Address
Byte (RAB), is the data to be written into the register specified by AR[6:0]. If AutoInc = 0, then another RAB is
expected from the master device, followed by another data byte, and so on.
CH7009
CH7009
CH7009
CH7009
CH7009
SD
acknowledge
acknowledge
acknowledge
acknowledge
acknowledge
I²C
SC
1-7
8
9
1-8
9
1-8
9
1-8
9
1-8
9
Start _{Device ID R/W* ACK RAB ACK Data ACK RAB ACK Data ACK}
Stop
Condition
Condition
Note: The acknowledge is from the CH7009 (slave).
Figure 11: Alternating Write Cycles
20
201-0000-035 Rev 1.1, 5/8/2000